GS

Gad Sheaffer

IN Intel: 68 patents #405 of 30,777Top 2%
Microsoft: 14 patents #2,856 of 40,388Top 8%
ED Empire Technology Development: 8 patents #72 of 547Top 15%
Overall (All Time): #17,646 of 4,157,543Top 1%
91
Patents All Time

Issued Patents All Time

Showing 25 most recent of 91 patents

Patent #TitleCo-InventorsDate
10229523 Augmented reality alteration detector Shmuel Ur, Shay Bushinsky, Vlad Grigore Dabija 2019-03-12
9836650 Identification of a photographer based on an image Shmuel Ur 2017-12-05
9785462 Registering a user-handler in hardware for transactional memory event handling Shlomo Raikin, Vadim Bassin 2017-10-10
9767027 Private memory regions and coherency optimization by controlling snoop traffic volume in multi-level cache hierarchy Jan Gray, David Callahn, Burton Smith, Ali-Reza Adl-Tabatabai 2017-09-19
9747221 Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform Boris Ginzburg, Ronny Ronen, Eliezer Weissmann 2017-08-29
9658880 Efficient garbage collection and exception handling in a hardware accelerated transactional memory system Jan Gray, Martin Taillefer, Yosseff Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs +2 more 2017-05-23
9626773 Augmented reality alteration detector Shmuel Ur, Shay Bushinsky, Vlad Grigore Dabija 2017-04-18
9619298 Scheduling computing tasks for multi-processor systems based on resource requirements Shmuel Ur 2017-04-11
9588771 Instruction set architecture-based inter-sequencer communications with a heterogeneous resource Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund +8 more 2017-03-07
9524240 Obscuring memory access patterns in conjunction with deadlock detection or avoidance Shay Gueron, Shlomo Raikin 2016-12-20
9477515 Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode Koichi Yamada, Landy Wang, Martin Taillefer, Arun U. Kishan, David Callahan +2 more 2016-10-25
9471129 Determining a write operation Shmuel Ur 2016-10-18
9459874 Instruction set architecture-based inter-sequencer communications with a heterogeneous resource Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund +8 more 2016-10-04
9430350 Instance monitor Shmuel Ur, David Hirshberg, Vlad Grigore Dabija, Shimon Gruper, Mordehai Margalit 2016-08-30
9350909 Remotely controlled crowd-sourced media capture Shmuel Ur, David Hirshberg, Yesha Sivan, Menahem Kaplan 2016-05-24
9280397 Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadata Ali-Reza Adl-Tabatabai, Bratin Saha, Jan Gray, David Callahan, Burton Smith +1 more 2016-03-08
9195600 Mechanisms to accelerate transactions using buffered stores Ali-Reza Adl-Tabatabai, Yang Ni, Bratin Saha, Vadim Bassin, David Callahan +1 more 2015-11-24
9164923 Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform Boris Ginzburg, Ronny Ronen, Eliezer Weissmann 2015-10-20
9100938 Digital relay for out of network devices Shmuel Ur 2015-08-04
9092253 Instrumentation of hardware assisted transactional memory system Martin Taillefer, Jan Gray, Richard Wurdack, Ali-Reza Adl Tabatabai 2015-07-28
9069670 Mechanisms to accelerate transactions using buffered stores Ali-Reza Adl-Tabatabai, Yang Ni, Bratin Saha, Vadim Bassin, David Callahan +1 more 2015-06-30
9003421 Acceleration threads on idle OS-visible thread execution units Ron Gabor, Avi Mendelson, Uri Weiser, Hong Wang 2015-04-07
8914618 Instruction set architecture-based inter-sequencer communications with a heterogeneous resource Hong Wang, John Shen, Hong Jiang, Richard Hankins, Per Hammarlund +8 more 2014-12-16
8886894 Mechanisms to accelerate transactions using buffered stores Ali-Reza Adl-Tabatabai, Yang Ni, Bratin Saha, Vadim Bassin, David Callahan +1 more 2014-11-11
8856466 Mechanisms to accelerate transactions using buffered stores Ali-Reza Adl-Tabatabai, Yang Ni, Bratin Saha, Vadim Bassin, David Callahan +1 more 2014-10-07