Issued Patents All Time
Showing 25 most recent of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11973697 | Composing diverse remote cores and FPGAs | — | 2024-04-30 |
| 11755484 | Instruction block allocation | Douglas C. Burger, Aaron L. Smith | 2023-09-12 |
| 11687345 | Out-of-order block-based processors and instruction schedulers using ready state data indexed by instruction position identifiers | Aaron L. Smith | 2023-06-27 |
| 11677662 | FPGA-efficient directional two-dimensional router | — | 2023-06-13 |
| 11455171 | Multiported parity scoreboard circuit | — | 2022-09-27 |
| 11449342 | Hybrid block-based processor and custom function blocks | Aaron L. Smith | 2022-09-20 |
| 11223573 | Shortcut routing on segmented directional torus interconnection networks | — | 2022-01-11 |
| 11106467 | Incremental scheduler for out-of-order block ISA processors | Aaron L. Smith | 2021-08-31 |
| 11048517 | Decoupled processor instruction window and operand buffer | Douglas C. Burger, Aaron L. Smith | 2021-06-29 |
| 10911352 | Multicast message delivery using a directional two-dimensional router and network | — | 2021-02-02 |
| 10587534 | Composing cores and FPGAS at massive scale with directional, two dimensional routers and interconnection networks | — | 2020-03-10 |
| 10419338 | Connecting diverse client cores using a directional two-dimensional router and network | — | 2019-09-17 |
| 10409599 | Decoding information about a group of instructions including a size of the group of instructions | Doug Burger, Aaron L. Smith | 2019-09-10 |
| 10409606 | Verifying branch targets | Douglas C. Burger, Aaron L. Smith | 2019-09-10 |
| 10346168 | Decoupled processor instruction window and operand buffer | Douglas C. Burger, Aaron L. Smith | 2019-07-09 |
| 10332008 | Parallel decision tree processor architecture | Douglas C. Burger, James R. Larus, Andrew R. Putnam | 2019-06-25 |
| 10175988 | Explicit instruction scheduler state information for a processor | Doug Burger, Aaron L. Smith | 2019-01-08 |
| 10116557 | Directional two-dimensional router and interconnection network for field programmable gate arrays, and other circuits and applications of the router and network | — | 2018-10-30 |
| 9952867 | Mapping instruction blocks based on block size | Douglas C. Burger, Aaron L. Smith | 2018-04-24 |
| 9946548 | Age-based management of instruction blocks in a processor instruction window | Douglas C. Burger, Aaron L. Smith | 2018-04-17 |
| 9767027 | Private memory regions and coherency optimization by controlling snoop traffic volume in multi-level cache hierarchy | David Callahn, Burton Smith, Gad Sheaffer, Ali-Reza Adl-Tabatabai | 2017-09-19 |
| 9720693 | Bulk allocation of instruction blocks to a processor instruction window | Douglas C. Burger, Aaron L. Smith | 2017-08-01 |
| 9658880 | Efficient garbage collection and exception handling in a hardware accelerated transactional memory system | Martin Taillefer, Yosseff Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs, Vinod Grover +2 more | 2017-05-23 |
| 9477515 | Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode | Koichi Yamada, Landy Wang, Martin Taillefer, Arun U. Kishan, David Callahan +2 more | 2016-10-25 |
| 9280397 | Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadata | Ali-Reza Adl-Tabatabai, Gad Sheaffer, Bratin Saha, David Callahan, Burton Smith +1 more | 2016-03-08 |