Issued Patents All Time
Showing 25 most recent of 127 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12412088 | Reducing operations for training neural networks | Maral Mesmakhosroshahi, Bita Darvish Rouhani, Eric S. Chung | 2025-09-09 |
| 12307372 | Data-aware model pruning for neural networks | Venmugil Elango, Bita Darvish Rouhani, Eric S. Chung, Maximilian Golub | 2025-05-20 |
| 12307355 | Neural network processing with chained instructions | Jeremy Fowers, Eric S. Chung | 2025-05-20 |
| 12190235 | System for training an artificial neural network | Maximilian Golub, Ritchie Zhao, Eric S. Chung, Bita Darvish Rouhani, Ge Yang +1 more | 2025-01-07 |
| 11977891 | Implicit program order | Aaron L. Smith | 2024-05-07 |
| 11899518 | Analog MAC aware DNN improvement | Gilad KIRSHENBOIM, Ran Sahar, Yehonathan REFAEL KALIM | 2024-02-13 |
| 11886833 | Hierarchical and shared exponent floating point data types | Bita Darvish Rouhani, Venmugil Elango, Rasoul SHAFIPOUR, Jeremy Fowers, Ming Liu +2 more | 2024-01-30 |
| 11803389 | Reach matrix scheduler circuit for scheduling instructions to be executed in a processor | Yusuf Cagatay Tekmen, Rodney Wayne Smith, Gagan Gupta, Kiran Ravi Seth | 2023-10-31 |
| 11755484 | Instruction block allocation | Jan Gray, Aaron L. Smith | 2023-09-12 |
| 11726912 | Coupling wide memory interface to wide write back paths | Aaron L. Smith, Gagan Gupta, David T. Harper | 2023-08-15 |
| 11681531 | Generation and use of memory access instruction order encodings | Aaron L. Smith | 2023-06-20 |
| 11676003 | Training neural network accelerators using mixed precision data formats | Bita Darvish Rouhani, Taesik Na, Eric S. Chung, Daniel Lo | 2023-06-13 |
| 11663450 | Neural network processing with chained instructions | Jeremy Fowers, Eric S. Chung | 2023-05-30 |
| 11645493 | Flow for quantized neural networks | Eric S. Chung, Bita Darvish Rouhani, Daniel Lo, Ritchie Zhao | 2023-05-09 |
| 11531552 | Executing multiple programs simultaneously on a processor core | Gagan Gupta | 2022-12-20 |
| 11494614 | Subsampling training data during artificial neural network training | Eric S. Chung, Bita Darvish Rouhani | 2022-11-08 |
| 11169991 | System and method for extracting and sharing application-related user data | Oriana Riva, Suman Kumar Nath, Earlence Fernandes | 2021-11-09 |
| 11157801 | Neural network processing with the neural network model pinned to on-chip memories of hardware nodes | Eric S. Chung, Jeremy Fowers, Kalin Ovtcharov | 2021-10-26 |
| 11144820 | Hardware node with position-dependent memories for neural network processing | Eric S. Chung, Jeremy Fowers | 2021-10-12 |
| 11132599 | Multi-function unit for programmable hardware nodes for neural network processing | Eric S. Chung, Jeremy Fowers | 2021-09-28 |
| 11126433 | Block-based processor core composition register | Aaron L. Smith | 2021-09-21 |
| 11099906 | Handling tenant requests in a system that uses hardware acceleration components | Derek Chiou, Sitaram V. Lanka | 2021-08-24 |
| 11048517 | Decoupled processor instruction window and operand buffer | Aaron L. Smith, Jan Gray | 2021-06-29 |
| 11016770 | Distinct system registers for logical processors | Aaron L. Smith | 2021-05-25 |
| 11010198 | Data processing system having a hardware acceleration plane and a software plane | Andrew R. Putnam, Stephen F. Heil | 2021-05-18 |