Issued Patents All Time
Showing 51–75 of 91 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8316194 | Mechanisms to accelerate transactions using buffered stores | Ali-Reza Adl-Tabatabai, Yang Ni, Bratin Saha, Vadim Bassin, David Callahan +1 more | 2012-11-20 |
| 8250331 | Operating system virtual memory management for hardware transactional memory | Koichi Yamada, Ali-Reza Adl-Tabatabai, Landy Wang, Martin Taillefer, Arun U. Kishan +3 more | 2012-08-21 |
| 8209689 | Live lock free priority scheme for memory transactions in transactional memory | Shlomo Raikin, Shay Gueron | 2012-06-26 |
| 8161247 | Wait loss synchronization | Jan Gray, David Callahan, Burton Smith, Ali-Reza Adl-Tabatabai, Bratin Saha | 2012-04-17 |
| 8140773 | Using ephemeral stores for fine-grained conflict detection in a hardware accelerated STM | Bratin Saha, Ali-Reza Adl-Tabatabai, Quinn A. Jacobson | 2012-03-20 |
| 8095824 | Performing mode switching in an unbounded transactional memory (UTM) system | Jan Gray, Martin Taillefer, Yossi Levanoni, Ali-Reza Adl-Tabatabai, Dave Detlefs +5 more | 2012-01-10 |
| 7991965 | Technique for using memory attributes | Quinn A. Jacobson, Anne W. Bracy, Hong Wang, John Shen, Per Hammarlund +6 more | 2011-08-02 |
| 7975129 | Selective hardware lock disabling | Shlomo Raikin, Doron Orenstlen | 2011-07-05 |
| 7958320 | Protected cache architecture and secure programming paradigm to protect applications | Shlomo Raikin, Shay Gueron | 2011-06-07 |
| 7613908 | Selective hardware lock disabling | Shlomo Raikin, Doron Orenstien | 2009-11-03 |
| 7587584 | Mechanism to exploit synchronization overhead to improve multithreaded performance | Natalie D. Enright, Jamison D. Collins, Perry Wang, Hong Wang, Xinmin Tran +2 more | 2009-09-08 |
| 7454601 | N-wide add-compare-select instruction | — | 2008-11-18 |
| 7437581 | Method and apparatus for varying energy per instruction according to the amount of available parallelism | Edward T. Grochowski, John Shen, Hong Wang, Doron Orenstein, Ronny Ronen +1 more | 2008-10-14 |
| 7293056 | Variable width, at least six-way addition/accumulation instructions | — | 2007-11-06 |
| 7260592 | Addressing mode and/or instruction for providing sine and cosine value pairs | — | 2007-08-21 |
| 7257728 | Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs | Jeffrey R. Wilcox | 2007-08-14 |
| 7028171 | Multi-way select instructions using accumulated condition codes | — | 2006-04-11 |
| 7007187 | Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs | Jeffrey R. Wilcox | 2006-02-28 |
| 6976049 | Method and apparatus for implementing single/dual packed multi-way addition instructions having accumulation options | — | 2005-12-13 |
| 6965962 | Method and system to overlap pointer load cache misses | — | 2005-11-15 |
| 6957321 | Instruction set extension using operand bearing NOP instructions | — | 2005-10-18 |
| 6944750 | Pre-steering register renamed instructions to execution unit associated locations in instruction cache | — | 2005-09-13 |
| 6928605 | Add-compare-select accelerator using pre-compare-select-add operation | — | 2005-08-09 |
| 6859851 | Buffer pre-loading for memory service interruptions | — | 2005-02-22 |
| 6779104 | Method and apparatus for pre-processing instructions for a processor | — | 2004-08-17 |