GS

Gad Sheaffer

IN Intel: 68 patents #405 of 30,777Top 2%
Microsoft: 14 patents #2,856 of 40,388Top 8%
ED Empire Technology Development: 8 patents #72 of 547Top 15%
📍 Haifa, OR: #1 of 9 inventorsTop 15%
Overall (All Time): #17,646 of 4,157,543Top 1%
91
Patents All Time

Issued Patents All Time

Showing 76–91 of 91 patents

Patent #TitleCo-InventorsDate
6732257 Reducing the length of lower level instructions by splitting and recombining an immediate 2004-05-04
6715064 Method and apparatus for performing sequential executions of elements in cooperation with a transform Reynold V. D'Sa, Slade Morgan, Alan B. Kyker, Gustavo P. Espinosa 2004-03-30
6593930 Method and apparatus to execute a memory maintenance operation during a screen blanking interval Opher Kahn 2003-07-15
6594754 Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters Stephan Jourdan, Ronny Ronen 2003-07-15
6539471 Method and apparatus for pre-processing instructions for a processor 2003-03-25
6515672 Managing prefetching from a data buffer Roman Surgutchik, Oded Lempel 2003-02-04
6470444 Method and apparatus for dividing a store operation into pre-fetch and store micro-operations 2002-10-22
6351802 Method and apparatus for constructing a pre-scheduled instruction cache 2002-02-26
6105124 Method and apparatus for merging binary translated basic blocks of instructions Yaron Farber, Robert Valentine 2000-08-15
6055630 System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units Reynold V. D'Sa, Alan B. Kyker, Gustavo P. Espinosa, Stavros Kalafatis, Rebecca E. Hebda 2000-04-25
5909573 Method of branch prediction using loop counters 1999-06-01
5838941 Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers Robert Valentine, Ronny Ronen, Ilan Spillinger, Adi Yoaz 1998-11-17
5818745 Computer for performing non-restoring division 1998-10-06
5790822 Method and apparatus for providing a re-ordered instruction cache in a pipelined microprocessor Ronny Ronen 1998-08-04
5784307 Division algorithm for floating point or integer numbers 1998-07-21
5710902 Instruction dependency chain indentifier Robert Valentine 1998-01-20