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Non-blocking simultaneous multithreading (NB-SMT) |
Gil Shomron |
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Tal Horowitz, Zuguang Wu, Huibin Luo, Yoni Choukroun |
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Resistive address decoder and virtually addressed memory |
Leonid Yavits, Ran Ginosar |
2020-12-29 |
| 10521237 |
Memristor based multithreading |
Avinoam Kolodny, Shahar Kvatinsky |
2019-12-31 |
| 10417005 |
Multi-multidimensional computer architecture for big data applications |
Tal Horowitz, Jintang Wang |
2019-09-17 |
| 9268729 |
Systems and methods for efficient handling of data traffic and processing within a processing device |
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| 9003421 |
Acceleration threads on idle OS-visible thread execution units |
Ron Gabor, Gad Sheaffer, Avi Mendelson, Hong Wang |
2015-04-07 |
| 8209457 |
Systems and methods for efficient handling of data traffic and processing within a processing device |
Yehiel Engel, Avraham Ganor, Tal Horowitz, Michael Chaim Schnarch, Yaron Shachar |
2012-06-26 |
| 7793032 |
Systems and methods for efficient handling of data traffic and processing within a processing device |
Yehiel Engel, Avraham Ganor, Tal Horowitz, Michael Chaim Schnarch, Yaron Shachar |
2010-09-07 |
| 5606676 |
Branch prediction and resolution apparatus for a superscalar computer processor |
Edward T. Grochowski, Donald B. Alpert, Jack Mills |
1997-02-25 |
| 5450605 |
Boundary markers for indicating the boundary of a variable length instruction to facilitate parallel processing of sequential instructions |
Edward T. Grochowski, Kenneth D. Shoemaker, Doron Orenstein |
1995-09-12 |
| 5442756 |
Branch prediction and resolution apparatus for a superscalar computer processor |
Edward T. Grochowski, Donald B. Alpert, Jack Mills |
1995-08-15 |
| 5381533 |
Dynamic flow instruction cache memory organized around trace segments independent of virtual address line |
Alexander Peleg |
1995-01-10 |
| 5265213 |
Pipeline system for executing predicted branch target instruction in a cycle concurrently with the execution of branch instruction |
David Hirsch Perlmutter, Yaakov Yaari |
1993-11-23 |
