Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10313236 | Method of flow based services for flash storage | Jon Livesey, Sharad Mehrotra, Thomas Gourley, Julian Ratcliffe | 2019-06-04 |
| 9973424 | Storage system with flow based services for flash storage | Jon Livesey, Sharad Mehrotra, Thomas Gourley, Julian Ratcliffe | 2018-05-15 |
| 9870154 | Network storage system using flash storage | Sharad Mehrotra, Chris Youngworth, Jon Livesey, Julian Ratcliffe, Tim Lieber +1 more | 2018-01-16 |
| 9509604 | Method of configuring a system for flow based services for flash storage and associated information structure | Jon Livesey, Sharad Mehrotra, Thomas Gourley, Julian Ratcliffe | 2016-11-29 |
| 9304902 | Network storage system using flash storage | Sharad Mehrotra, Chris Youngworth, Jon Livesey, Julian Ratcliff, Tim Lieber +1 more | 2016-04-05 |
| 9286225 | Flash-based storage system including reconfigurable circuitry | Sharad Mehrotra, Thomas Gourley, Jon Livesey | 2016-03-15 |
| 6205544 | Decomposition of instructions into branch and sequential code sections | Christopher B. Wilkerson | 2001-03-20 |
| 6119218 | Method and apparatus for prefetching data in a computer system | Judge K. Arora, Jerome C. Huck | 2000-09-12 |
| 5991874 | Conditional move using a compare instruction generating a condition field | Donald B. Alpert | 1999-11-23 |
| 5948095 | Method and apparatus for prefetching data in a computer system | Judge K. Arora, Jerome C. Huck | 1999-09-07 |
| 5915117 | Computer architecture for the deferral of exceptions on speculative instructions | Jonathan Ross, James O. Hays, Stephen G. Burger, Dale Morris, Carol L. Thompson +4 more | 1999-06-22 |
| 5889984 | Floating point and integer condition compatibility for conditional branches and conditional moves | — | 1999-03-30 |
| 5859999 | System for restoring predicate registers via a mask having at least a single bit corresponding to a plurality of registers | Dale Morris | 1999-01-12 |
| 5606676 | Branch prediction and resolution apparatus for a superscalar computer processor | Edward T. Grochowski, Donald B. Alpert, Uri Weiser | 1997-02-25 |
| 5559986 | Interleaved cache for multiple accesses per clock cycle in a microprocessor | Donald B. Alpert, Mustafiz R. Choudhury | 1996-09-24 |
| 5442756 | Branch prediction and resolution apparatus for a superscalar computer processor | Edward T. Grochowski, Donald B. Alpert, Uri Weiser | 1995-08-15 |