Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6430670 | Apparatus and method for a virtual hashed page table | William R. Bryg, James O. Hays, John M. Kessenich, Jonathan Ross, Gary N. Hammond +2 more | 2002-08-06 |
| 6408373 | Method and apparatus for pre-validating regions in a virtual addressing scheme | James O. Hays, Jonathan Ross, William R. Bryg, Rajiv Gupta, Gary N. Hammond +1 more | 2002-06-18 |
| 6393544 | Method and apparatus for calculating a page table index from a virtual address | William R. Bryg, Gary N. Hammond, James O. Hays, Jerome C. Huck, Jonathan Ross +2 more | 2002-05-21 |
| 6286095 | Computer apparatus having special instructions to force ordered load and store operations | Dale Morris, Barry J. Flahive, Michael L. Ziegler, Jerome C. Huck, Ruby B. Lee +2 more | 2001-09-04 |
| 6230248 | Method and apparatus for pre-validating regions in a virtual addressing scheme | James O. Hays, Jonathan Ross, William R. Bryg, Rajiv Gupta, Gary N. Hammon +1 more | 2001-05-08 |
| 6216214 | Apparatus and method for a virtual hashed page table | William R. Bryg, James O. Hays, John M. Kessenich, Jonathan Ross, Gary N. Hammond +2 more | 2001-04-10 |
| 6199144 | Method and apparatus for transferring data in a computer system | Judge K. Arora, William R. Bryg, Gary N. Hammond, Michael L. Ziegler | 2001-03-06 |
| 6128706 | Apparatus and method for a load bias--load with intent to semaphore | William R. Bryg, Gary N. Hammond, Michael L. Ziegler | 2000-10-03 |
| 6088780 | Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address | Koichi Yamada, Gary N. Hammond, Jim Hays, Jonathan Ross, William R. Bryg | 2000-07-11 |
| 6079012 | Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory | Dale Morris, Bernard L. Stumpf, Barry J. Flahive, Jeffrey D. Kurtze, Ruby B. Lee +1 more | 2000-06-20 |
| 6006325 | Method and apparatus for instruction and data serialization in a computer processor | Gary N. Hammond, William R. Bryg | 1999-12-21 |
| 5940872 | Software and hardware-managed translation lookaside buffer | Gary N. Hammond, Koichi Yamada, James O. Hays, Jonathan Ross, William R. Bryg | 1999-08-17 |
| 5915117 | Computer architecture for the deferral of exceptions on speculative instructions | Jonathan Ross, Jack Mills, James O. Hays, Dale Morris, Carol L. Thompson +4 more | 1999-06-22 |
| 5784708 | Translation mechanism for input/output addresses | K. Monroe Bridges, Robert J. Brooks, William R. Bryg, Michael L. Ziegler | 1998-07-21 |
| 5535352 | Access hints for input/output address translation mechanisms | K. Monroe Bridges, Robert J. Brooks, William R. Bryg, Eric Hamilton, Helen Nusbaum +2 more | 1996-07-09 |
| 5515522 | Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache | K. Monroe Bridges, William R. Bryg, James M. Hull, Michael L. Ziegler | 1996-05-07 |
| 5278985 | Software method for implementing dismissible instructions on a computer | Daryl Odnert, Michael J. Mahon, Dale Morris, Jerome C. Huck, Ruby B. Lee +2 more | 1994-01-11 |