Issued Patents All Time
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8464009 | Method for memory interleave support with a ceiling mask | Ramaswamy Sivaramakrishnan, Connie W. Cheung | 2013-06-11 |
| 7103728 | System and method for memory migration in distributed-memory multi-processor systems | Debendra Das Sharma, Ashish Gupta | 2006-09-05 |
| 6874070 | System and method for memory interleaving using cell map with entry grouping for higher-way interleaving | Ashish Gupta | 2005-03-29 |
| 6820086 | Forming linked lists using content addressable memory | Sorin Iacobovici, Joseph H. Hassoun | 2004-11-16 |
| 6430670 | Apparatus and method for a virtual hashed page table | Stephen G. Burger, James O. Hays, John M. Kessenich, Jonathan Ross, Gary N. Hammond +2 more | 2002-08-06 |
| 6408373 | Method and apparatus for pre-validating regions in a virtual addressing scheme | Stephen G. Burger, James O. Hays, Jonathan Ross, Rajiv Gupta, Gary N. Hammond +1 more | 2002-06-18 |
| 6393544 | Method and apparatus for calculating a page table index from a virtual address | Stephen G. Burger, Gary N. Hammond, James O. Hays, Jerome C. Huck, Jonathan Ross +2 more | 2002-05-21 |
| 6304932 | Queue-based predictive flow control mechanism with indirect determination of queue fullness | Michael L. Ziegler, Robert J. Brooks, Craig R. Frink, Thomas R. Hotchkiss, Robert D. Odineal +2 more | 2001-10-16 |
| 6230248 | Method and apparatus for pre-validating regions in a virtual addressing scheme | Stephen G. Burger, James O. Hays, Jonathan Ross, Rajiv Gupta, Gary N. Hammon +1 more | 2001-05-08 |
| 6216214 | Apparatus and method for a virtual hashed page table | Stephen G. Burger, James O. Hays, John M. Kessenich, Jonathan Ross, Gary N. Hammond +2 more | 2001-04-10 |
| 6199144 | Method and apparatus for transferring data in a computer system | Judge K. Arora, Stephen G. Burger, Gary N. Hammond, Michael L. Ziegler | 2001-03-06 |
| 6182176 | Queue-based predictive flow control mechanism | Michael L. Ziegler, Robert J. Brooks, Craig R. Frink, Thomas R. Hotchkiss, Robert D. Odineal +2 more | 2001-01-30 |
| 6128706 | Apparatus and method for a load bias--load with intent to semaphore | Stephen G. Burger, Gary N. Hammond, Michael L. Ziegler | 2000-10-03 |
| 6108721 | Method and apparatus for ensuring data consistency between an i/o channel and a processor | Monish Shah, Thomas Spencer, IV | 2000-08-22 |
| 6088780 | Page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address | Koichi Yamada, Gary N. Hammond, Jim Hays, Jonathan Ross, Stephen G. Burger | 2000-07-11 |
| 6079012 | Computer that selectively forces ordered execution of store and load operations between a CPU and a shared memory | Dale Morris, Bernard L. Stumpf, Barry J. Flahive, Jeffrey D. Kurtze, Stephen G. Burger +1 more | 2000-06-20 |
| 6049851 | Method and apparatus for checking cache coherency in a computer architecture | Kenneth K. Chan, Eric Delano, John F. Shelton | 2000-04-11 |
| 6006325 | Method and apparatus for instruction and data serialization in a computer processor | Stephen G. Burger, Gary N. Hammond | 1999-12-21 |
| 5995967 | Forming linked lists using content addressable memory | Sorin Iacobovici, Joseph H. Hassoun | 1999-11-30 |
| 5940872 | Software and hardware-managed translation lookaside buffer | Gary N. Hammond, Koichi Yamada, Stephen G. Burger, James O. Hays, Jonathan Ross | 1999-08-17 |
| 5784708 | Translation mechanism for input/output addresses | K. Monroe Bridges, Robert J. Brooks, Stephen G. Burger, Michael L. Ziegler | 1998-07-21 |
| 5724538 | Computer memory address control apparatus utilizing hashed address tags in page tables which are compared to a combined address tag and index which are longer than the basic data width of the associated computer | Dale Morris, Jerome C. Huck | 1998-03-03 |
| 5603004 | Method for decreasing time penalty resulting from a cache miss in a multi-level cache system | Gordon Kurpanek, Eric Delano, Michael Buckley | 1997-02-11 |
| 5586274 | Atomic operation control scheme | Craig R. Frink, Larry N. McMahan, Helen Nusbaum | 1996-12-17 |
| 5586297 | Partial cache line write transactions in a computing system with a write back cache | Robert J. Brooks, Eric Hamilton, Michael L. Ziegler | 1996-12-17 |