Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
MS

Monish Shah — 30 Patents

Microsoft: 13 patents #3,175 of 40,388Top 8%
HP: 8 patents #2,426 of 16,619Top 15%
Google: 8 patents #3,283 of 22,993Top 15%
CLCnex Labs: 1 patents #9 of 13Top 70%
Dublin, CA: #63 of 1,312 inventorsTop 5%
California: #17,345 of 386,348 inventorsTop 5%
Overall (All Time): #121,623 of 4,157,543Top 3%
30 Patents All Time
Monish Shah has been granted 30 US patents while listed as an inventor at Microsoft. The first was granted in 1990 and the most recent in October 2024. Monish Shah ranks #121,623 of 4,157,543 US inventors in our database (top 2.9%). Patent records list Monish Shah in Dublin, CA, US.

Patents per Year

Patents granted per year, 1990 to 2024Bar chart with a peak of 4 patents in 2022.peak 41990: 1 patents19901992: 1 patents1993: 1 patents19931998: 2 patents2000: 1 patents20002001: 1 patents2006: 1 patents20062016: 1 patents2018: 2 patents20182019: 3 patents2020: 2 patents20202021: 2 patents2022: 4 patents20222023: 4 patents2024: 4 patents2024

Issued Patents All Time

Showing 1–25 of 30 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12111726 Error rates for memory with built in error correction and detection 2024-10-08 $356,986,000
12079084 Distributed raid for parity-based flash storage devices 2024-09-03 $243,844,000
12056372 Collecting quality of service statistics for in-use child physical functions of multiple physical function non-volatile memory devices Scott Chao-Chueh Lee, Lei Kou, Brenda Wai Yan Bell 2024-08-06 $310,621,000
11977785 Non-volatile memory device-assisted live migration of virtual machine data Scott Chao-Chueh Lee, Lei Kou, Liang Yang, Yimin Deng, Martijn de Kort 2024-05-07 $460,452,000
11775442 Memory system with a predictable read latency from media with a long write latency John G. Bennett 2023-10-03 $205,636,000
11726909 Two-way interleaving in a three-rank environment Brett K. Dodds 2023-08-15 $266,941,000
11656981 Memory reduction in a system by oversubscribing physical memory shared by compute entities supported by the system Lisa R. Hsu, Daniel Sebastian BERGER 2023-05-23 $326,580,000
11640334 Error rates for memory with built in error correction and detection 2023-05-02 $605,587,000
11455239 Memory reduction in a system by oversubscribing physical memory shared by compute entities supported by the system Lisa R. Hsu, Daniel Sebastian BERGER 2022-09-27 $211,764,000
11429523 Two-way interleaving in a three-rank environment Brett K. Dodds 2022-08-30 $157,926,000
11422886 Die level data redundancy in solid state storage devices Chenfeng Zhang, Vamsi Sata 2022-08-23 $222,819,000
11269779 Memory system with a predictable read latency from media with a long write latency John G. Bennett 2022-03-08 $166,683,000
11150825 Adaptive spare block usage in solid state drives Abhilash Ravi Kashyap 2021-10-19 $230,268,000
10942849 Use of a logical-to-logical translation map and a logical-to-physical translation map to access a data storage device Christopher J. Sabol, Slava Pestov, Thomas Wyatt Craig, Manuel Benitez, Daniel Ari Ehrenberg 2021-03-09 $109,767,000
10866755 Two stage command buffers to overlap IOMMU map and second tier memory reads Benjamin C. Serebrin, Albert T. Borchers 2020-12-15 $58,660,000
10606484 NAND flash storage device with NAND buffer 2020-03-31 $39,178,000
10482009 Use of a logical-to-logical translation map and a logical-to-physical translation map to access a data storage device Christopher J. Sabol, Slava Pestov, Thomas Wyatt Craig, Manuel Benitez, Daniel Ari Ehrenberg 2019-11-19 $38,332,000
10459847 Non-volatile memory device application programming interface Albert T. Borchers, Joel Dylan Coburn, Benjamin C. Serebrin 2019-10-29 $29,755,000
10296256 Two stage command buffers to overlap IOMMU map and second tier memory reads Benjamin C. Serebrin, Albert T. Borchers 2019-05-21 $26,266,000
9940230 Compression and decompression of data at high speed in solid state storage 2018-04-10
9880778 Memory devices and methods 2018-01-30 $16,228,000
9436595 Use of application data and garbage-collected data to improve write efficiency of a data storage device Manuel Benitez 2016-09-06 $12,831,000
7035981 Asynchronous input/output cache having reduced latency Thomas Spencer, IV 2006-04-25 $11,316,000
6279081 System and method for performing memory fetches for an ATM card Thomas Spencer, IV, Robert J. Horning 2001-08-21 $35,985,000
6108721 Method and apparatus for ensuring data consistency between an i/o channel and a processor William R. Bryg, Thomas Spencer, IV 2000-08-22 $102,575,000