Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12111726 | Error rates for memory with built in error correction and detection | — | 2024-10-08 |
| 12079084 | Distributed raid for parity-based flash storage devices | — | 2024-09-03 |
| 12056372 | Collecting quality of service statistics for in-use child physical functions of multiple physical function non-volatile memory devices | Scott Chao-Chueh Lee, Lei Kou, Brenda Wai Yan Bell | 2024-08-06 |
| 11977785 | Non-volatile memory device-assisted live migration of virtual machine data | Scott Chao-Chueh Lee, Lei Kou, Liang Yang, Yimin Deng, Martijn de Kort | 2024-05-07 |
| 11775442 | Memory system with a predictable read latency from media with a long write latency | John G. Bennett | 2023-10-03 |
| 11726909 | Two-way interleaving in a three-rank environment | Brett K. Dodds | 2023-08-15 |
| 11656981 | Memory reduction in a system by oversubscribing physical memory shared by compute entities supported by the system | Lisa R. Hsu, Daniel Sebastian BERGER | 2023-05-23 |
| 11640334 | Error rates for memory with built in error correction and detection | — | 2023-05-02 |
| 11455239 | Memory reduction in a system by oversubscribing physical memory shared by compute entities supported by the system | Lisa R. Hsu, Daniel Sebastian BERGER | 2022-09-27 |
| 11429523 | Two-way interleaving in a three-rank environment | Brett K. Dodds | 2022-08-30 |
| 11422886 | Die level data redundancy in solid state storage devices | Chenfeng Zhang, Vamsi Sata | 2022-08-23 |
| 11269779 | Memory system with a predictable read latency from media with a long write latency | John G. Bennett | 2022-03-08 |
| 11150825 | Adaptive spare block usage in solid state drives | Abhilash Ravi Kashyap | 2021-10-19 |
| 10942849 | Use of a logical-to-logical translation map and a logical-to-physical translation map to access a data storage device | Christopher J. Sabol, Slava Pestov, Thomas Wyatt Craig, Manuel Benitez, Daniel Ari Ehrenberg | 2021-03-09 |
| 10866755 | Two stage command buffers to overlap IOMMU map and second tier memory reads | Benjamin C. Serebrin, Albert T. Borchers | 2020-12-15 |
| 10606484 | NAND flash storage device with NAND buffer | — | 2020-03-31 |
| 10482009 | Use of a logical-to-logical translation map and a logical-to-physical translation map to access a data storage device | Christopher J. Sabol, Slava Pestov, Thomas Wyatt Craig, Manuel Benitez, Daniel Ari Ehrenberg | 2019-11-19 |
| 10459847 | Non-volatile memory device application programming interface | Albert T. Borchers, Joel Dylan Coburn, Benjamin C. Serebrin | 2019-10-29 |
| 10296256 | Two stage command buffers to overlap IOMMU map and second tier memory reads | Benjamin C. Serebrin, Albert T. Borchers | 2019-05-21 |
| 9940230 | Compression and decompression of data at high speed in solid state storage | — | 2018-04-10 |
| 9880778 | Memory devices and methods | — | 2018-01-30 |
| 9436595 | Use of application data and garbage-collected data to improve write efficiency of a data storage device | Manuel Benitez | 2016-09-06 |
| 7035981 | Asynchronous input/output cache having reduced latency | Thomas Spencer, IV | 2006-04-25 |
| 6279081 | System and method for performing memory fetches for an ATM card | Thomas Spencer, IV, Robert J. Horning | 2001-08-21 |
| 6108721 | Method and apparatus for ensuring data consistency between an i/o channel and a processor | William R. Bryg, Thomas Spencer, IV | 2000-08-22 |