Issued Patents All Time
Showing 25 most recent of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405904 | Sharing memory and I/O services between nodes | Robert G. Blankenship, Suresh Chittor, Kenneth C. Creta, Balint Fleischer, Michelle C. Jen +2 more | 2025-09-02 |
| 12386768 | Extending multichip package link off package | Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss | 2025-08-12 |
| 11526784 | Real-time server capacity optimization tool using maximum predicted value of resource utilization determined based on historica data and confidence interval | Suki Ramasamy, Mahesh Ganesan, Vipul Chaudhari, Srinivasan Bhaskaran Kasyap | 2022-12-13 |
| 11288154 | Adjustable retimer buffer | Daniel S. Froelich | 2022-03-29 |
| 10860449 | Adjustable retimer buffer | Daniel S. Froelich | 2020-12-08 |
| 10747688 | Low latency retimer | Michelle C. Jen, Venkatraman Iyer, Tao Liang | 2020-08-18 |
| 10503684 | Multiple uplink port devices | Anil Vasudevan, David J. Harriman | 2019-12-10 |
| 10248591 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2019-04-02 |
| 10198394 | Reduced pin count interface | Michelle C. Jen, Dan Froelich, Bruce A. Tennant, Quinn Devine, Su Wei Lim | 2019-02-05 |
| 10146733 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Jeffrey C. Swanson | 2018-12-04 |
| 9977618 | Pooling of memory resources across multiple nodes | Mohan J. Kumar, Balint Fleischer | 2018-05-22 |
| 9921768 | Low power entry in a shared memory link | Michelle C. Jen, Mahesh Wagh, Venkatraman Iyer | 2018-03-20 |
| 9552253 | Probabilistic flit error checking | Venkatraman Iyer, Robert G. Blankenship | 2017-01-24 |
| 9355058 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Jeffrey C. Swanson | 2016-05-31 |
| 9229897 | Embedded control channel for high speed serial interconnect | Venkatraman Iyer, Robert G. Blankenship, Darren S. Jue | 2016-01-05 |
| 9208121 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Fulvio Spagna, Jeffrey C. Swanson | 2015-12-08 |
| 9183171 | Fast deskew when exiting low-power partial-width high speed link state | Venkatraman Iyer, Robert G. Blankenship, Darren S. Jue | 2015-11-10 |
| 8793404 | Atomic operations | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, David J. Harriman, Mark Rosenbluth +13 more | 2014-07-29 |
| 8782318 | Increasing Input Output Hubs in constrained link based multi-processor systems | Chandra P. Joshi, Gurushankar Rajamani | 2014-07-15 |
| 8549183 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, David J. Harriman, Mark Rosenbluth +13 more | 2013-10-01 |
| 8230119 | PCI express enhancements and extensions | Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, David J. Harriman, Mark Rosenbluth +13 more | 2012-07-24 |
| 8209563 | Strategy to verify asynchronous links across chips | Gurushankar Rajamani, Hanh Hoang | 2012-06-26 |
| 8111704 | Multiple compression techniques for packetized information | Abhishek Singhal, Jesus Palomino, Mario A. Rubio | 2012-02-07 |
| 7958404 | Enabling resynchronization of a logic analyzer | Keith A. Drescher, David Sams, Richard Glass | 2011-06-07 |
| 7836352 | Method and apparatus for improving high availability in a PCI express link through predictive failure analysis | Surena Neshvad, Guru Rajamani, Hanh Hoang | 2010-11-16 |