Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12353340 | Systems for high-speed computing using an optical interchange | Horia Alexandru Toma, Zuowei Shen, William Frank Edwards, Hong Liu, Ilyas Mohammed | 2025-07-08 |
| 12242338 | Memory sparing to improve chip reliability | Horia Alexandru Toma, Le Wang, Spoorthy Nanjaiah, Albert Forte Magyar, Xiaoming Wang | 2025-03-04 |
| 12132802 | Off-chip memory backed reliable transport connection cache hardware architecture | Weihuang Wang, Srinivas Vaduvatha, Xiaoming Wang, Abhishek Agarwal, Jiazhen Zheng +1 more | 2024-10-29 |
| 11934826 | Vector reductions using shared scratchpad memory | Thomas Norrie, Andrew Everett Phelps, Matthew Leever Hedlund, Norman Paul Jouppi | 2024-03-19 |
| 11928580 | Interleaving memory requests to accelerate memory accesses | Alice Kuo | 2024-03-12 |
| 11748028 | Data processing on memory controller | Amin Farmahini, Benjamin Steel Gelb, Sukalpa Biswas | 2023-09-05 |
| 11513724 | Data processing on memory controller | Amin Farmahini, Benjamin Steel Gelb, Sukalpa Biswas | 2022-11-29 |
| 11295206 | Interleaving memory requests to accelerate memory accesses | Alice Kuo | 2022-04-05 |
| 11182159 | Vector reductions using shared scratchpad memory | Thomas Norrie, Andrew Everett Phelps, Matthew Leever Hedlund, Norman Paul Jouppi | 2021-11-23 |
| 11137936 | Data processing on memory controller | Amin Farmahini, Benjamin Steel Gelb, Sukalpa Biswas | 2021-10-05 |
| 9594713 | Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media | Randall Pascarella, Jaya Prakash Subramaniam Ganasan, Thuong Quang Truong, Joseph Gerald McDonald, Thomas Philip Speier | 2017-03-14 |
| 9164943 | Self correction logic for serial-to-parallel converters | Anil Sharma, Kanaka Lakshimi Siva Prasad Gadey Naga Venkata | 2015-10-20 |
| 8782318 | Increasing Input Output Hubs in constrained link based multi-processor systems | Debendra Das Sharma, Chandra P. Joshi | 2014-07-15 |
| 8209563 | Strategy to verify asynchronous links across chips | Debendra Das Sharma, Hanh Hoang | 2012-06-26 |
| 7770051 | Strategy to verify asynchronous links across chips | Debendra Das Sharma, Hanh Hoang | 2010-08-03 |
| 7464287 | Strategy to verify asynchronous links across chips | Debendra Das Sharma, Hanh Hoang | 2008-12-09 |
| 6810372 | Multimodal optimization technique in test generation | Manoj Unnikrishnan | 2004-10-26 |