Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12216558 | Test and measurement system for analyzing devices under test | Sam J. Strickling, Michelle L. Baldwin, Jonathan San, Lin-Yung Chen | 2025-02-04 |
| 12135581 | System, method, and apparatus for SRIS mode selection for PCIE | David J. Harriman, Debendra Das Sharma, Sean O. Stalley | 2024-11-05 |
| 12117486 | Systems, methods and devices for high-speed input/output margin testing | Shane A. Hazzard, Sarah R. Boen, Jed H. Andrews | 2024-10-15 |
| 12061232 | Margin test data tagging and predictive expected margins | Sam J. Strickling, Michelle L. Baldwin, Jonathan San, Lin-Yung Chen | 2024-08-13 |
| 12055584 | Systems, methods, and devices for high-speed input/output margin testing | Sam J. Strickling | 2024-08-06 |
| 12055603 | Cable condition indicator | Sam J. Strickling, Michelle L. Baldwin, Jonathan San, Lin-Yung Chen | 2024-08-06 |
| 11946970 | Systems, methods and devices for high-speed input/output margin testing | Shane A. Hazzard, Sarah R. Boen, Jed H. Andrews | 2024-04-02 |
| 11940483 | Systems, methods and devices for high-speed input/output margin testing | Sam J. Strickling, Michelle L. Baldwin, Jonathan San, Lin-Yung Chen | 2024-03-26 |
| 11927627 | Systems, methods, and devices for high-speed input/output margin testing | Sam J. Strickling | 2024-03-12 |
| 11782809 | Test and measurement system for analyzing devices under test | Sam J. Strickling, Michelle L. Baldwin, Jonathan San, Lin-Yung Chen | 2023-10-10 |
| 11675003 | Interconnect retimer enhancements | Debendra Das Sharma | 2023-06-13 |
| 11630480 | System, method, and apparatus for SRIS mode selection for PCIe | David J. Harriman, Debendra Das Sharma, Sean O. Stalley | 2023-04-18 |
| 11327861 | Cross-talk generation in a multi-lane link during lane testing | Debendra Das Sharma | 2022-05-10 |
| 11288154 | Adjustable retimer buffer | Debendra Das Sharma | 2022-03-29 |
| 11157350 | In-band margin probing on an operational interconnect | Debendra Das Sharma, Fulvio Spagna, Per E. Fornberg, David Edward Bradley | 2021-10-26 |
| 10860449 | Adjustable retimer buffer | Debendra Das Sharma | 2020-12-08 |
| 10853212 | Cross-talk generation in a multi-lane link during lane testing | Debendra Das Sharma | 2020-12-01 |
| 10706003 | Reduced pin count interface | Michelle C. Jen, Debendra Das Sharma, Bruce A. Tennant, Quinn Devine, Su Wei Lim | 2020-07-07 |
| 10671476 | In-band margin probing on an operational interconnect | Debendra Das Sharma, Fulvio Spagna, Per E. Fornberg, David Edward Bradley | 2020-06-02 |
| 10534034 | Interconnect retimer enhancements | Debendra Das Sharma | 2020-01-14 |
| 9946683 | Reducing precision timing measurement uncertainty | David J. Harriman | 2018-04-17 |
| 9779053 | Physical interface for a serial interconnect | Debendra Das Sharma, Venkatraman Iyer, Michelle C. Jen, Rahul R. Shah, Eric M. Lee | 2017-10-03 |
| 9558145 | Method, apparatus and system for measuring latency in a physical unit of a circuit | David J. Harriman, Mahesh Wagh, Abdul R. Ismail | 2017-01-31 |
| 9552269 | Test logic for a serial interconnect | Debendra Das Sharma | 2017-01-24 |
| 9262347 | Method, apparatus and system for measuring latency in a physical unit of a circuit | David J. Harriman, Mahesh Wagh, Abdul R. Ismail | 2016-02-16 |