Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12197357 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2025-01-14 |
| 12189550 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2025-01-07 |
| 11789892 | Recalibration of PHY circuitry for the PCI express (PIPE) interface based on using a message bus interface | Michelle C. Jen, Minxi Gao, Debendra Das Sharma, Bruce A. Tennant, Noam Dolev Geldbard | 2023-10-17 |
| 11741030 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2023-08-29 |
| 11327920 | Recalibration of PHY circuitry for the PCI express (pipe) interface based on using a message bus interface | Michelle C. Jen, Minxi Gao, Debendra Das Sharma, Bruce A. Tennant, Noam Dolev Geldbard | 2022-05-10 |
| 11269793 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2022-03-08 |
| 11157350 | In-band margin probing on an operational interconnect | Daniel S. Froelich, Debendra Das Sharma, Per E. Fornberg, David Edward Bradley | 2021-10-26 |
| 10931329 | High speed interconnect with channel extension | Rahul R. Shah, William R. Halleck, Venkatraman Iyer | 2021-02-23 |
| 10909055 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Ashish Gupta | 2021-02-02 |
| 10713209 | Recalibration of PHY circuitry for the PCI Express (PIPE) interface based on using a message bus interface | Michelle C. Jen, Minxi Gao, Debendra Das Sharma, Bruce A. Tennant, Noam Dolev Geldbard | 2020-07-14 |
| 10671476 | In-band margin probing on an operational interconnect | Daniel S. Froelich, Debendra Das Sharma, Per E. Fornberg, David Edward Bradley | 2020-06-02 |
| 10523411 | Programmable clock data recovery (CDR) system including multiple phase error control paths | Shenggao Li, Ji Chen, Michael De Vita, Guluke Tong | 2019-12-31 |
| 10380046 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Ashish Gupta | 2019-08-13 |
| 10374616 | Phase frequency detector | Wenyan Jia, Shenggao Li | 2019-08-06 |
| 10284210 | Open-loop voltage regulation and drift compensation for digitally controlled oscillator (DCO) | Shenggao Li, Guluke Tong, Sujatha B. Gowder | 2019-05-07 |
| 10248591 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2019-04-02 |
| 10146733 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Debendra Das Sharma, Jeffrey C. Swanson | 2018-12-04 |
| 9985637 | Phase frequency detector | Wenyan Jia, Shenggao Li | 2018-05-29 |
| 9916266 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Ashish Gupta | 2018-03-13 |
| 9692589 | Redriver link testing | Venkatraman Iyer, Debendra Das Sharma | 2017-06-27 |
| 9626321 | High performance interconnect | Robert J. Safranek, Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers +18 more | 2017-04-18 |
| 9596108 | Method and apparatus for baud-rate timing recovery | Sitaraman V. Iyer | 2017-03-14 |
| 9531393 | Phase frequency detector | Wenyan Jia, Shenggao Li | 2016-12-27 |
| 9455727 | Open-loop voltage regulation and drift compensation for digitally controlled oscillator (DCO) | Shenggao Li, Guluke Tong, Sujatha B. Gowder | 2016-09-27 |
| 9418035 | High performance interconnect physical layer | Venkatraman Iyer, Darren S. Jue, Robert G. Blankenship, Ashish Gupta | 2016-08-16 |