Issued Patents All Time
Showing 25 most recent of 73 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423108 | Devices transferring cache lines, including metadata on external links | — | 2025-09-23 |
| 12197357 | High performance interconnect | Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more | 2025-01-14 |
| 12189550 | High performance interconnect | Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more | 2025-01-07 |
| 11880686 | Devices transferring cache lines, including metadata on external links | — | 2024-01-23 |
| 11868209 | Method and system for sequencing data checks in a packet | Matthew Robert Erler, Robert J. Toepfer, Sandeep Brahmadathan, Shailendra Ramrao Chavan, Jonglih Yu | 2024-01-09 |
| 11741030 | High performance interconnect | Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more | 2023-08-29 |
| 11481270 | Method and system for sequencing data checks in a packet | Matthew Robert Erler, Robert J. Toepfer, Sandeep Brahmadathan, Shailendra Ramrao Chavan, Jonglih Yu | 2022-10-25 |
| 11269793 | High performance interconnect | Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more | 2022-03-08 |
| 11061850 | Multiple transaction data flow control unit for high-speed interconnect | Robert G. Blankenship, Debendra Das Sharma | 2021-07-13 |
| 11003610 | Multichip package link | Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Gerald Pasdast, Ananthan Ayyasamy +2 more | 2021-05-11 |
| 10552357 | Multichip package link | Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Gerald Pasdast, Ananthan Ayyasamy +2 more | 2020-02-04 |
| 10503688 | Multiple transaction data flow control unit for high-speed interconnect | Robert G. Blankenship, Debendra Das Sharma | 2019-12-10 |
| 10365965 | High performance interconnect link layer | Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson | 2019-07-30 |
| 10360098 | High performance interconnect link layer | Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson | 2019-07-23 |
| 10268583 | High performance interconnect coherence protocol resolving conflict based on home transaction identifier different from requester transaction identifier | Robert Beers, Robert G. Blankenship, Jeff Willey, Robert A. Maddox, Aaron T. Spink | 2019-04-23 |
| 10248591 | High performance interconnect | Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more | 2019-04-02 |
| 10204064 | Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field | Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson | 2019-02-12 |
| 10078617 | Multiple transaction data flow control unit for high-speed interconnect | Robert G. Blankenship, Debendra Das Sharma | 2018-09-18 |
| 10073808 | Multichip package link | Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Gerald Pasdast, Ananthan Ayyasamy +2 more | 2018-09-11 |
| 10019366 | Satisfying memory ordering requirements between partial reads and non-snoop accesses | Robert Beers, Ching-Tsun Chou, James Vash | 2018-07-10 |
| 9813998 | Techniques for entering a low-power link state | Shaun M. Conrad, Selim Bilgin | 2017-11-07 |
| 9785556 | Cross-die interface snoop or global observation message ordering | Ramacharan Sundararaman, Tracey L. Gustafson | 2017-10-10 |
| 9753885 | Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field | Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson | 2017-09-05 |
| 9703712 | Satisfying memory ordering requirements between partial reads and non-snoop accesses | Robert Beers, Ching-Tsun Chou, James Vash | 2017-07-11 |
| 9626321 | High performance interconnect | Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more | 2017-04-18 |