Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Robert J. Safranek — 73 Patents

Intel: 43 patents #801 of 30,777Top 3%
ATAT&T: 19 patents #870 of 18,772Top 5%
ACAmpere Computing: 4 patents #13 of 94Top 15%
IBM: 4 patents #21,783 of 70,183Top 35%
SSSequent Computer Systems: 3 patents #1 of 33Top 4%
Portland, OR: #203 of 9,213 inventorsTop 3%
Oregon: #387 of 28,073 inventorsTop 2%
Overall (All Time): #26,958 of 4,157,543Top 1%
73 Patents All Time
Robert J. Safranek has been granted 73 US patents while listed as an inventor at Intel. The first was granted in 1991 and the most recent in September 2025. Robert J. Safranek ranks #26,958 of 4,157,543 US inventors in our database (top 0.65%). Patent records list Robert J. Safranek in Portland, OR, US.

Issued Patents All Time

Showing 1–25 of 73 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12423108 Devices transferring cache lines, including metadata on external links 2025-09-23
12197357 High performance interconnect Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more 2025-01-14
12189550 High performance interconnect Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more 2025-01-07
11880686 Devices transferring cache lines, including metadata on external links 2024-01-23
11868209 Method and system for sequencing data checks in a packet Matthew Robert Erler, Robert J. Toepfer, Sandeep Brahmadathan, Shailendra Ramrao Chavan, Jonglih Yu 2024-01-09
11741030 High performance interconnect Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more 2023-08-29 $19,273,000
11481270 Method and system for sequencing data checks in a packet Matthew Robert Erler, Robert J. Toepfer, Sandeep Brahmadathan, Shailendra Ramrao Chavan, Jonglih Yu 2022-10-25
11269793 High performance interconnect Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more 2022-03-08 $16,017,000
11061850 Multiple transaction data flow control unit for high-speed interconnect Robert G. Blankenship, Debendra Das Sharma 2021-07-13 $34,958,000
11003610 Multichip package link Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Gerald Pasdast, Ananthan Ayyasamy +2 more 2021-05-11 $38,242,000
10552357 Multichip package link Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Gerald Pasdast, Ananthan Ayyasamy +2 more 2020-02-04 $21,361,000
10503688 Multiple transaction data flow control unit for high-speed interconnect Robert G. Blankenship, Debendra Das Sharma 2019-12-10 $22,400,000
10365965 High performance interconnect link layer Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson 2019-07-30 $29,864,000
10360098 High performance interconnect link layer Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson 2019-07-23 $32,139,000
10268583 High performance interconnect coherence protocol resolving conflict based on home transaction identifier different from requester transaction identifier Robert Beers, Robert G. Blankenship, Jeff Willey, Robert A. Maddox, Aaron T. Spink 2019-04-23 $25,127,000
10248591 High performance interconnect Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more 2019-04-02 $26,887,000
10204064 Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson 2019-02-12 $25,597,000
10078617 Multiple transaction data flow control unit for high-speed interconnect Robert G. Blankenship, Debendra Das Sharma 2018-09-18 $29,867,000
10073808 Multichip package link Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Gerald Pasdast, Ananthan Ayyasamy +2 more 2018-09-11 $19,778,000
10019366 Satisfying memory ordering requirements between partial reads and non-snoop accesses Robert Beers, Ching-Tsun Chou, James Vash 2018-07-10 $30,438,000
9813998 Techniques for entering a low-power link state Shaun M. Conrad, Selim Bilgin 2017-11-07 $13,901,000
9785556 Cross-die interface snoop or global observation message ordering Ramacharan Sundararaman, Tracey L. Gustafson 2017-10-10 $9,084,000
9753885 Multislot link layer flit wherein flit includes three or more slots whereby each slot comprises respective control field and respective payload field Jeff Willey, Robert G. Blankenship, Jeffrey C. Swanson 2017-09-05 $9,844,000
9703712 Satisfying memory ordering requirements between partial reads and non-snoop accesses Robert Beers, Ching-Tsun Chou, James Vash 2017-07-11 $8,311,000
9626321 High performance interconnect Robert G. Blankenship, Venkatraman Iyer, Jeff Willey, Robert Beers, Darren S. Jue +18 more 2017-04-18 $8,310,000