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USPTO Patent Rankings Data through Dec 31, 2025
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Gerald Pasdast — 50 Patents

Intel: 50 patents #641 of 30,777Top 3%
San Jose, CA: #978 of 32,062 inventorsTop 4%
California: #8,040 of 386,348 inventorsTop 3%
Overall (All Time): #53,743 of 4,157,543Top 2%
50 Patents All Time
Gerald Pasdast has been granted 50 US patents while listed as an inventor at Intel. The first was granted in 2001 and the most recent in December 2025. Gerald Pasdast ranks #53,743 of 4,157,543 US inventors in our database (top 1.3%). Patent records list Gerald Pasdast in San Jose, CA, US.

Issued Patents All Time

Showing 1–25 of 50 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12505065 On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHY Debendra Das Sharma, Narasimha Lanka, Peter Z. Onufryk, Swadesh Choudhary, Zuoguo Wu +2 more 2025-12-23
12500583 Clock interpolation system for eye-centering Jayen Desai, Pengyin WANG, Debendra Das Sharma 2025-12-16
12499074 Die-to-die interconnect protocol layer Debendra Das Sharma, Swadesh Choudhary, Narasimha Lanka, Lakshmi Narasimhan Seshan, Zuoguo Wu 2025-12-16
12499019 Retimers to extend a die-to-die interconnect Debendra Das Sharma, Swadesh Choudhary, Sridhar Muthrasanallur, Narasimha Lanka, Zuoguo Wu +1 more 2025-12-16
12481614 Standard interfaces for die to die (D2D) interconnect stacks Debendra Das Sharma, Swadesh Choudhary, Narasimha Lanka, Zuoguo Wu, Lakshmi Narasimhan Seshan 2025-11-25
12468597 Valid signal for latency sensitive die-to-die (D2D) interconnects Narasimha Lanka, Debendra Das Sharma, Lakshmi Narasimhan Seshan, Swadesh Choudhary, Zuoguo Wu 2025-11-11
12469820 Fine-grained disaggregated server architecture Carleton L. Molnar, Adel A. Elsherbini, Tanay Karnik, Shawna M. Liff, Robert J. Munoz +6 more 2025-11-11
12405912 Link initialization training and bring up for die-to-die interconnect Narasimha Lanka, Lakshmipriya Seshan, Swadesh Choudhary, Debendra Das Sharma, Zuoguo Wu 2025-09-02
12406962 Power delivery through capacitor-dies in a multi-layered microelectronic assembly Adel A. Elsherbini, William J. Lambert, Krishna Bharath, Shawna M. Liff, Nicolas Butzen +4 more 2025-09-02
12362284 Composite interposer structure and method of providing same Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan 2025-07-15
12362306 Clock-gating in die-to-die (D2D) interconnects Narasimha Lanka, Debendra Das Sharma, Lakshmipriya Seshan, Zuoguo Wu, Swadesh Choudhary 2025-07-15
12353305 Compliance and debug testing of a die-to-die interconnect Swadesh Choudhary, Narasimha Lanka, Debendra Das Sharma, Lakshmipriya Seshan, Zuoguo Wu 2025-07-08
12332826 Die-to-die interconnect Debendra Das Sharma, Swadesh Choudhary, Narasimha Lanka, Lakshmipriya Seshan, Zuoguo Wu 2025-06-17
12321305 Sideband interface for die-to-die interconnects Narasimha Lanka, Swadesh Choudhary, Debendra Das Sharma, Lakshmipriya Seshan, Zuoguo Wu 2025-06-03
12316343 PHY-based retry techniques for die-to-die interfaces Narasimha Lanka, Lakshmipriya Seshan, Debendra Das Sharma, Zuoguo Wu 2025-05-27
12315794 Skip level vias in metallization layers for integrated circuit devices Adel A. Elsherbini, Mauro J. Kobrinsky, Shawna M. Liff, Johanna M. Swan, Sathya Narasimman Tiagaraj 2025-05-27
12306216 Dynamic voltage regulator sensing for chiplet-based designs Vikrant Thigle, Vijay Anand Mathiyalagan, Anand Haridass, Arun Chandrasekhar 2025-05-20
12288746 Skip level vias in metallization layers for integrated circuit devices Adel A. Elsherbini, Mauro J. Kobrinsky, Shawna M. Liff, Johanna M. Swan, Sathya Narasimman Tiagaraj 2025-04-29
12266682 Capacitors and resistors at direct bonding interfaces in microelectronic assemblies Adel A. Elsherbini, Mohammad Enamul Kabir, Zhiguo Qian, Kimin Jun, Shawna M. Liff +3 more 2025-04-01
12164319 Dual loop voltage regulator Sathya Narasimman Tiagaraj, Edward A. Burton 2024-12-10 $13,394,000
12159840 Scalable and interoperable PHYLESS die-to-die IO solution Zhiguo Qian, Juan Zeng, Peipei Wang, Ahmad Siddiqui, Lakshmipriya Seshan 2024-12-03 $28,395,000
12117960 Approximate data bus inversion technique for latency sensitive applications Narasimha Lanka, Lakshmipriya Seshan, Zuoguo Wu 2024-10-15 $19,078,000
12107060 Microelectronic assemblies with inductors in direct bonding regions Adel A. Elsherbini, Zhiguo Qian, Mohammad Enamul Kabir, Han Wui Then, Kimin Jun +5 more 2024-10-01 $20,560,000
12100662 Power-forwarding bridge for inter-chip data signal transfer Zhiguo Qian, Peipei Wang, Daniel Scott Krueger, Edward A. Burton 2024-09-24 $33,787,000
12062631 Microelectronic assemblies with inductors in direct bonding regions Adel A. Elsherbini, Krishna Bharath, Kevin P. O'Brien, Kimin Jun, Han Wui Then +5 more 2024-08-13 $26,861,000