Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10410975 | Processed wafer of scalable electrical circuits, method for making same, and device comprising scaled electrical circuits | Bruce Scatchard, Chunfang Xie | 2019-09-10 |
| 10230396 | Method and apparatus for layer-specific LDPC decoding | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie | 2019-03-12 |
| 9813080 | Layer specific LDPC decoder | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie | 2017-11-07 |
| 9590656 | System and method for higher quality log likelihood ratios in LDPC decoding | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie, Ihab Jaser, Luca Crippa | 2017-03-07 |
| 9454414 | System and method for accumulating soft information in LDPC decoding | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie, Ihab Jaser, Luca Crippa | 2016-09-27 |
| 9448881 | Memory controller and integrated circuit device for correcting errors in data read from memory cells | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie, Ihab Jaser | 2016-09-20 |
| 9397701 | System and method for lifetime specific LDPC decoding | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie | 2016-07-19 |
| 9235467 | System and method with reference voltage partitioning for low density parity check decoding | Rino Micheloni, Alessia Marelli | 2016-01-12 |
| 9146890 | Method and apparatus for mapped I/O routing in an interconnect switch | David Alan Brown | 2015-09-29 |
| 9128858 | Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie, Ihab Jaser | 2015-09-08 |
| 9092353 | Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie, Ihab Jaser | 2015-07-28 |
| 9025495 | Flexible routing engine for a PCI express switch and method of use | David Alan Brown, Cesar A. Talledo | 2015-05-05 |
| 8995302 | Method and apparatus for translated routing in an interconnect switch | David Alan Brown, Cesar A. Talledo | 2015-03-31 |
| 8990661 | Layer specific attenuation factor LDPC decoder | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie | 2015-03-24 |
| 8707122 | Nonvolatile memory controller with two-stage error correction technique for enhanced reliability | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie | 2014-04-22 |
| 8694849 | Shuffler error correction code system and method | Rino Micheloni, Alessia Marelli | 2014-04-08 |
| 8656257 | Nonvolatile memory controller with concatenated error correction codes | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie | 2014-02-18 |
| 8656071 | System and method for routing a data message through a message network | Ganesh T. Seshan | 2014-02-18 |
| 8621318 | Nonvolatile memory controller with error detection for concatenated error correction codes | Rino Micheloni, Alessia Marelli, Christopher I. W. Norrie | 2013-12-31 |
| 8601346 | System and method for generating parity data in a nonvolatile memory controller by using a distributed processing technique | Inna Levit | 2013-12-03 |
| 8588228 | Nonvolatile memory controller with host controller interface for retrieving and dispatching nonvolatile memory commands in a distributed manner | Jayesh Patel, Ihab Jaser, Ganesh T. Seshan | 2013-11-19 |
| 8554968 | Interrupt technique for a nonvolatile memory controller | Jayesh Patel, Ihab Jaser | 2013-10-08 |
| 8429325 | PCI express switch and method for multi-port non-transparent switching | Cesar A. Talledo | 2013-04-23 |
| 8397144 | BCH data correction system and method | Christopher I. W. Norrie, Alessia Marelli, Rino Micheloni | 2013-03-12 |
| 8170007 | Packet telephony appliance | Mike Chan, Charles D. Cranor, Raman Gopalakrishnan, Laurence W. Ruedisueli, Cormac John Sreenan | 2012-05-01 |