Issued Patents All Time
Showing 25 most recent of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12175116 | Method and apparatus for gather/scatter operations in a vector processor | — | 2024-12-24 |
| 11782871 | Method and apparatus for desynchronizing execution in a vector processor | — | 2023-10-10 |
| 10230396 | Method and apparatus for layer-specific LDPC decoding | Rino Micheloni, Alessia Marelli, Peter Z. Onufryk | 2019-03-12 |
| 9813080 | Layer specific LDPC decoder | Rino Micheloni, Alessia Marelli, Peter Z. Onufryk | 2017-11-07 |
| 9590656 | System and method for higher quality log likelihood ratios in LDPC decoding | Rino Micheloni, Alessia Marelli, Peter Z. Onufryk, Ihab Jaser, Luca Crippa | 2017-03-07 |
| 9454414 | System and method for accumulating soft information in LDPC decoding | Rino Micheloni, Alessia Marelli, Peter Z. Onufryk, Ihab Jaser, Luca Crippa | 2016-09-27 |
| 9448881 | Memory controller and integrated circuit device for correcting errors in data read from memory cells | Rino Micheloni, Alessia Marelli, Peter Z. Onufryk, Ihab Jaser | 2016-09-20 |
| 9450610 | High quality log likelihood ratios determined using two-index look-up table | Rino Micheloni, Alessia Marelli | 2016-09-20 |
| 9397701 | System and method for lifetime specific LDPC decoding | Rino Micheloni, Peter Z. Onufryk, Alessia Marelli | 2016-07-19 |
| 9235488 | System and method for random noise generation | — | 2016-01-12 |
| 9128858 | Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values | Rino Micheloni, Peter Z. Onufryk, Alessia Marelli, Ihab Jaser | 2015-09-08 |
| 9092353 | Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system | Rino Micheloni, Peter Z. Onufryk, Alessia Marelli, Ihab Jaser | 2015-07-28 |
| 8990661 | Layer specific attenuation factor LDPC decoder | Rino Micheloni, Peter Z. Onufryk, Alessia Marelli | 2015-03-24 |
| 8984365 | System and method for reduced memory storage in LDPC decoding | — | 2015-03-17 |
| 8984376 | System and method for avoiding error mechanisms in layered iterative decoding | — | 2015-03-17 |
| 8935598 | System and method for adaptive check node approximation in LDPC decoding | — | 2015-01-13 |
| 8707122 | Nonvolatile memory controller with two-stage error correction technique for enhanced reliability | Rino Micheloni, Peter Z. Onufryk, Alessia Marelli | 2014-04-22 |
| 8656257 | Nonvolatile memory controller with concatenated error correction codes | Rino Micheloni, Alessia Marelli, Peter Z. Onufryk | 2014-02-18 |
| 8621318 | Nonvolatile memory controller with error detection for concatenated error correction codes | Rino Micheloni, Alessia Marelli, Peter Z. Onufryk | 2013-12-31 |
| 8397144 | BCH data correction system and method | Alessia Marelli, Rino Micheloni, Peter Z. Onufryk | 2013-03-12 |
| 8327243 | System and method for generating locator polynomials | — | 2012-12-04 |
| 8285884 | Data aggregation system and method for deskewing data at selectable data rates | — | 2012-10-09 |
| 8161210 | Multi-queue system and method for deskewing symbols in data streams | — | 2012-04-17 |
| 8069392 | Error correction code system and method | — | 2011-11-29 |
| 7995696 | System and method for deskewing data transmitted through data lanes | — | 2011-08-09 |