Issued Patents All Time
Showing 26–44 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7848319 | Programmably sliceable switch-fabric unit and methods of use | Matthew D. Ornes, Gene Chui, Onchuen (Daryn) Lau | 2010-12-07 |
| 7779197 | Device and method for address matching with post matching limit check and nullification | Lambert Fong | 2010-08-17 |
| 7756014 | Device and method for handling catastrophic routing | — | 2010-07-13 |
| 7734977 | Method and system for error correction over serial link | Matthew D. Ornes, Gene Chui | 2010-06-08 |
| 7694025 | Method and device for base address sorting and entry into base address registers | — | 2010-04-06 |
| 7647438 | Binary base address sorting method and device with shift vector | Christopher Bergen, Robert J. Divivier, Thomas Norrie | 2010-01-12 |
| 7634586 | Device for concurrent limit validity check | — | 2009-12-15 |
| 7454554 | Binary base address search device and method | Christopher Bergen, Robert J. Divivier, Thomas Norrie | 2008-11-18 |
| 7356722 | Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits | Onchuen (Daryn) Lau, Matthew D. Ornes, Chris D. Bergen, Robert J. Divivier, Gene Chui +1 more | 2008-04-08 |
| 7263097 | Programmably sliceable switch-fabric unit and methods of use | Matthew D. Ornes, Gene Chui, Onchuen (Daryn) Lau | 2007-08-28 |
| 7181485 | Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits | Onchuen (Daryn) Lau, Matthew D. Ornes, Chris D. Bergen, Robert J. Divivier, Gene Chui +1 more | 2007-02-20 |
| 7079485 | Multiservice switching system with distributed switch fabric | Onchuen (Daryn) Lau, Chris D. Bergen, Robert J. Divivier, Gene Chui, Matthew D. Ornes +1 more | 2006-07-18 |
| 6748567 | Method and system for error correction over serial link | Matthew D. Ornes, Gene Chui | 2004-06-08 |
| 6311298 | Mechanism to simplify built-in self test of a control store unit | — | 2001-10-30 |
| 6223257 | Instruction cache address generation technique having reduced delays in fetching missed data | Sean Cummins, Kenneth K. Munson, Matthew D. Ornes | 2001-04-24 |
| 6172623 | Efficient bit scan mechanism | Dzung Tran | 2001-01-09 |
| 5490255 | Expedited execution of pipelined command having self-ordering operand processing requirements | Stephen J. Rawlinson | 1996-02-06 |
| 5408674 | System for checking the validity of two byte operation code by mapping two byte operation codes into control memory in order to reduce memory size | Carolee N. Newcomb, Peter K. Yu | 1995-04-18 |
| 5386549 | Error recovery system for recovering errors that occur in control store in a computer system employing pipeline architecture | Carolee V. Newcomb, Peter K. Yu, Allan J. Zmyslowski | 1995-01-31 |