| 5517514 |
Parity checking system with reduced usage of I/O pins |
Chris Norrie, Luis Ancajas, Carolee V. Newcomb |
1996-05-14 |
| 5426783 |
System for processing eight bytes or less by the move, pack and unpack instruction of the ESA/390 instruction set |
Chris Norrie, Stephen J. Rawlinson |
1995-06-20 |
| 5420997 |
Memory having concurrent read and writing from different addresses |
Gary Browning, Edward G. Ryba |
1995-05-30 |
| 5386549 |
Error recovery system for recovering errors that occur in control store in a computer system employing pipeline architecture |
Christopher I. W. Norrie, Carolee V. Newcomb, Peter K. Yu |
1995-01-31 |
| 5355470 |
Method for reconfiguring individual timer registers offline |
Jon Lexau, Quang Huy Nguyen, Robert Shaw, Carolee V. Newcomb |
1994-10-11 |
| 5325520 |
Invoking hardware recovery actions via action latches |
Quang Huy Nguyen, Arun Shah |
1994-06-28 |
| 5210832 |
Multiple domain emulation system with separate domain facilities which tests for emulated instruction exceptions before completion of operand fetch cycle |
Robert M. Maier, John C. Andoh, Arno S. Krakauer, Richard J. Tobias |
1993-05-11 |
| 4967351 |
Central processor architecture implementing deterministic early condition code analysis using digit based, subterm computation and selective subterm combination |
Pat Y. Hom |
1990-10-30 |
| 4888689 |
Apparatus and method for improving cache access throughput in pipelined processors |
Michael D. Taylor, Robert M. Maier, Michael J. Begley, Jeffrey A. Thomas, Joseph Anthony Petolino, Jr. |
1989-12-19 |
| 4855947 |
Microprogrammable pipeline interlocks based on the validity of pipeline states |
Robert M. Maier |
1989-08-08 |
| 4812989 |
Method for executing machine language instructions |
Robert M. Maier, Carolee N. Schober |
1989-03-14 |
| 4785392 |
Addressing multiple storage spaces |
Robert M. Maier, John C. Andoh, Arno S. Krakauer, Richard J. Tobias |
1988-11-15 |