Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12279056 | Raw scaler with chromatic aberration correction | Guy Cote, Simon Wolfenden Butler, Joseph P. Bratt | 2025-04-15 |
| 12041365 | Raw scaler with chromatic aberration correction | Guy Cote, Simon Wolfenden Butler, Joseph P. Bratt | 2024-07-16 |
| 11653118 | Raw scaler with chromatic aberration correction | Guy Cote, Simon Wolfenden Butler, Joseph P. Bratt | 2023-05-16 |
| 10694129 | Raw scaler with chromatic aberration correction | Guy Cote, Simon Wolfenden Butler, Joseph P. Bratt | 2020-06-23 |
| 9743057 | Systems and methods for lens shading correction | Guy Cote, Suk Hwan Lim, D. Amnon Silverstein | 2017-08-22 |
| 8872946 | Systems and methods for raw image processing | Guy Cote, Sheng Lin, Suk Hwan Lim, D. Amnon Silverstein, David Hayward +2 more | 2014-10-28 |
| 8386748 | Address translation unit with multiple virtual queues | — | 2013-02-26 |
| 8316212 | Translation lookaside buffer (TLB) with reserved areas for specific sources | — | 2012-11-20 |
| 8108650 | Translation lookaside buffer (TLB) with reserved areas for specific sources | — | 2012-01-31 |
| 5958041 | Latency prediction in a pipelined microarchitecture | William L. Lynch, Gary R. Lauterbach, Chitresh Narasimhaiah | 1999-09-28 |
| 5928355 | Apparatus for reducing instruction issue stage stalls through use of a staging register | — | 1999-07-27 |
| 5918034 | Method for decoupling pipeline stages | — | 1999-06-29 |
| 5898852 | Load instruction steering in a dual data cache microarchitecture | William L. Lynch, Gary R. Lauterbach, Kalon S. Holdbrook | 1999-04-27 |
| 5838946 | Method and apparatus for accomplishing processor read of selected information through a cache memory | — | 1998-11-17 |
| 5784603 | Fast handling of branch delay slots on mispredicted branches | Arthur T. Leung | 1998-07-21 |
| 5761722 | Method and apparatus for solving the stale data problem occurring in data access performed with data caches | Sanjay Vishin | 1998-06-02 |
| 5283890 | Cache memory arrangement with write buffer pipeline providing for concurrent cache determinations | Emil W. Brown, III | 1994-02-01 |
| 5095424 | Computer system architecture implementing split instruction and operand cache line-pair-state management | Gary A. Woffinden, Theodore S. Robinson, Jeffrey A. Thomas, Robert A. Ertl, James P. Millar +4 more | 1992-03-10 |
| 4888689 | Apparatus and method for improving cache access throughput in pipelined processors | Michael D. Taylor, Robert M. Maier, Michael J. Begley, Allan J. Zmyslowski, Jeffrey A. Thomas | 1989-12-19 |
| 4872111 | Monolithic semi-custom IC having standard LSI sections and coupling gate array sections | Kevin L. Daberkow, Christopher D. Finan, Daniel Carl Sobottka, Jeffrey A. Thomas | 1989-10-03 |
| 4855904 | Cache storage queue | Kevin L. Daberkow, Christopher D. Finan, Daniel Carl Sobottka, Jeffrey A. Thomas | 1989-08-08 |
| 4852100 | Error detection and correction scheme for main storage unit | Harold F. Christensen, Jeffrey A. Thomas, Jeffrey Isozaki | 1989-07-25 |
| 4851993 | Cache move-in bypass | Jack Chen, Jeffrey A. Thomas, Michael J. Begley, Ajay K. Shah, Michael D. Taylor +1 more | 1989-07-25 |
| 4780809 | Apparatus for storing data with deferred uncorrectable error reporting | Gary A. Woffinden | 1988-10-25 |
| 4768197 | Cache error code update | Christopher D. Finan, Jeffrey Isozaki, Nicholas Y. Pang | 1988-08-30 |