Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5457781 | System having main unit for shutting off clocks to memory upon completion of writing data into memory and information supervising unit to read the data | Eddie Collins | 1995-10-10 |
| 5297276 | Method and apparatus for maintaining deterministic behavior in a first synchronous system which responds to inputs from nonsynchronous second system | Eddie Collins, Ronald G. Weber, Clifford A. Petersen | 1994-03-22 |
| 5168560 | Microprocessor system private split cache tag stores with the system tag store having a different validity bit for the same data line | Theodore S. Robinson, Jeffrey A. Thomas, Robert A. Ertl, Ajay K. Shah | 1992-12-01 |
| 5095424 | Computer system architecture implementing split instruction and operand cache line-pair-state management | Gary A. Woffinden, Theodore S. Robinson, Jeffrey A. Thomas, Robert A. Ertl, Christopher D. Finan +4 more | 1992-03-10 |