Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9094237 | Packet routing and switching device | Peter Malcolm Barnes, Nikhil Jayaram, Anthony Joseph Li, Sharad Mehrotra | 2015-07-28 |
| 8270399 | Crossbar apparatus for a forwarding table memory in a router | John C. Holst | 2012-09-18 |
| 8270401 | Packet routing and switching device | Peter Malcolm Barnes, Nikhil Jayaram, Anthony Joseph Li, Sharad Mehrotra | 2012-09-18 |
| 7852852 | Method for compressing route data in a router | Srihari Ramachandra Sangli | 2010-12-14 |
| 7710991 | Scalable packet routing and switching device and method | Anthony Joseph Li, Peter Malcolm Barnes | 2010-05-04 |
| 7706386 | Fast 2-key scheduler | Sha Ma, Brian Alleyne | 2010-04-27 |
| 7554914 | System and method for adaptively balancing network traffic over router output ports | Anthony Joseph Li | 2009-06-30 |
| 7525904 | Redundant packet routing and switching device and method | Anthony Joseph Li, Peter Malcolm Barnes | 2009-04-28 |
| 7489689 | Method, system and apparatus for scheduling a large pool of resources | Sha Ma | 2009-02-10 |
| 7453883 | Method for compressing route data in a router | Srihari Ramachandra Sangli | 2008-11-18 |
| 7450438 | Crossbar apparatus for a forwarding table memory in a router | John C. Holst | 2008-11-11 |
| 7418536 | Processor having systolic array pipeline for processing data packets | Arthur T. Leung, Anthony Joseph Li, Sharad Mehrotra | 2008-08-26 |
| 7382787 | Packet routing and switching device | Peter Malcolm Barnes, Nikhil Jayaram, Anthony Joseph Li, Sharad Mehrotra | 2008-06-03 |
| 7069372 | Processor having systolic array pipeline for processing data packets | Arthur T. Leung, Anthony Joseph Li, Sharad Mehrotra | 2006-06-27 |
| 6487715 | Dynamic code motion optimization and path tracing | Joseph I. Chamdani, Gary R. Lauterbach | 2002-11-26 |
| 6317810 | Microprocessor having a prefetch cache | Herbert Lopez-Aguado, Denise Chiacchia, Gary R. Lauterbach | 2001-11-13 |
| 6164840 | Ensuring consistency of an instruction cache with a store cache check and an execution blocking flush instruction in an instruction queue | — | 2000-12-26 |
| 6078587 | Mechanism for coalescing non-cacheable stores | Michael G. Lavelle | 2000-06-20 |
| 6076147 | Non-inclusive cache system using pipelined snoop bus | Al Yamauchi | 2000-06-13 |
| 6061766 | Non-inclusive cache method using pipelined snoop bus | Al Yamauchi | 2000-05-09 |
| 6016532 | Method for handling data cache misses using help instructions | Gary R. Lauterbach | 2000-01-18 |
| 5958041 | Latency prediction in a pipelined microarchitecture | Joseph Anthony Petolino, Jr., Gary R. Lauterbach, Chitresh Narasimhaiah | 1999-09-28 |
| 5900018 | Processor-implemented method of controlling data access to shared resource via exclusive access control write-cache | — | 1999-05-04 |
| 5898852 | Load instruction steering in a dual data cache microarchitecture | Joseph Anthony Petolino, Jr., Gary R. Lauterbach, Kalon S. Holdbrook | 1999-04-27 |
| 5878252 | Microprocessor configured to generate help instructions for performing data cache fills | Gary R. Lauterbach | 1999-03-02 |