Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6408377 | Dynamic allocation of resources in multiple microprocessor pipelines | — | 2002-06-18 |
| 6341343 | Parallel processing instructions routed through plural differing capacity units of operand address generators coupled to multi-ported memory and ALUs | — | 2002-01-22 |
| 6304954 | Executing multiple instructions in multi-pipelined processor by dynamically switching memory ports of fewer number than the pipeline | — | 2001-10-16 |
| 6289439 | Method, device and microprocessor for performing an XOR clear without executing an XOR instruction | Peter C. Mills | 2001-09-11 |
| 6263424 | Execution of data dependent arithmetic instructions in multi-pipeline processors | Dzung Tran | 2001-07-17 |
| 6263427 | Branch prediction mechanism | Sean Cummins | 2001-07-17 |
| 6233675 | Facility to allow fast execution of and, or, and test instructions | Peter C. Mills | 2001-05-15 |
| 6223257 | Instruction cache address generation technique having reduced delays in fetching missed data | Sean Cummins, Christopher I. W. Norrie, Matthew D. Ornes | 2001-04-24 |