Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Peter C. Mills — 25 Patents

NVIDIA: 23 patents #250 of 7,811Top 4%
RCRise Technology Co.: 2 patents #4 of 19Top 25%
San Jose, CA: #2,531 of 32,062 inventorsTop 8%
California: #22,079 of 386,348 inventorsTop 6%
Overall (All Time): #158,593 of 4,157,543Top 4%
25 Patents All Time
Peter C. Mills has been granted 25 US patents while listed as an inventor at NVIDIA. The first was granted in 2001 and the most recent in October 2023. Peter C. Mills ranks #158,593 of 4,157,543 US inventors in our database (top 3.8%). Patent records list Peter C. Mills in San Jose, CA, US.

Issued Patents All Time

Showing 1–25 of 25 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11789811 Techniques for storing data to enhance recovery and detection of data corruption errors Michael Sullivan, Nirmal Saxena, John Brooks 2023-10-17 $613,841,000
11720440 Error containment for enabling local checkpoint and recovery Naveen Cherukuri, Saurabh Hukerikar, Paul Racunas, Nirmal Saxena, David Charles Patrick +10 more 2023-08-08 $2,376,795,000
11474897 Techniques for storing data to enhance recovery and detection of data corruption errors Michael Sullivan, Nirmal Saxena, John Brooks 2022-10-18 $483,516,000
10423424 Replicated stateless copy engine Lincoln G. Garlick, Philip Browning Johnson, Rafal Zboinski, Jeff Tuckey, Samuel H. Duncan 2019-09-24
10152328 Systems and methods for voting among parallel threads John R. Nickolls, Lars Nyland, Jeremy Sugerman, Timothy Foley, Brian Fahs +2 more 2018-12-11 $143,375,000
9639365 Indirect function call instructions in a synchronous parallel thread processor Brett W. Coon, John R. Nickolls, Lars Nyland, John Erik Lindholm 2017-05-02 $52,442,000
9407427 Technique for optimizing the phase of a data signal transmitted across a communication link Gregory Kodani, Guatam Bhatia 2016-08-02 $41,366,000
9184907 Flexible threshold counter for clock-and-data recovery Gautam Bhatia 2015-11-10 $11,691,000
8645638 Shared single-access memory with management of multiple parallel requests Brett W. Coon, Ming Y. Siu, Weizhong Xu, Stuart F. Oberman, John R. Nickolls 2014-02-04 $4,726,000
8578387 Dynamic load balancing of instructions for execution by heterogeneous processing engines Stuart F. Oberman, John Erik Lindholm, Samuel Liu 2013-11-05 $12,817,000
8375176 Lock mechanism to enable atomic updates to shared memory Brett W. Coon, John R. Nickolls, Lars Nyland 2013-02-12 $6,282,000
8312254 Indirect function call instructions in a synchronous parallel thread processor Brett W. Coon, John R. Nickolls, Lars Nyland, John Erik Lindholm 2012-11-13 $16,728,000
8225076 Scoreboard having size indicators for tracking sequential destination register usage in a multi-threaded processor Brett W. Coon, Stuart F. Oberman, Ming Y. Siu 2012-07-17 $12,933,000
8214625 Systems and methods for voting among parallel threads John R. Nickolls, Lars Nyland, Jeremy Sugerman, Timothy Foley, Brian Fahs +2 more 2012-07-03 $8,387,000
8200947 Systems and methods for voting among parallel threads John R. Nickolls, Lars Nyland, Jeremy Sugerman, Timothy Foley, Brian Fahs +2 more 2012-06-12 $6,265,000
8176265 Shared single-access memory with management of multiple parallel requests Brett W. Coon, Ming Y. Siu, Weizhong Xu, Stuart F. Oberman, John R. Nickolls 2012-05-08 $15,544,000
8108625 Shared memory with parallel access and access conflict resolution mechanism Brett W. Coon, Ming Y. Siu, Weizhong Xu, Stuart F. Oberman, John R. Nickolls 2012-01-31 $9,973,000
8055856 Lock mechanism to enable atomic updates to shared memory Brett W. Coon, John R. Nickolls, Lars Nyland 2011-11-08 $16,490,000
7949855 Scheduler in multi-threaded processor prioritizing instructions passing qualification rule John Erik Lindholm, Brett W. Coon, Gary M. Tarolli, John Burgess 2011-05-24 $30,945,000
7788468 Synchronization of threads in a cooperative thread array John R. Nickolls, Stephen D. Lew, Brett W. Coon 2010-08-31 $15,743,000
7761697 Processing an indirect branch instruction in a SIMD architecture Brett W. Coon, John Erik Lindholm, John R. Nickolls 2010-07-20 $8,420,000
7434032 Tracking register usage during multithreaded processing using a scoreboard having separate memory regions and storing sequential register size indicators Brett W. Coon, Stuart F. Oberman, Ming Y. Siu 2008-10-07 $13,081,000
7366878 Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better caching John Erik Lindholm, Brett W. Coon, Gary M. Tarolli, John Burgess 2008-04-29 $34,790,000
6289439 Method, device and microprocessor for performing an XOR clear without executing an XOR instruction Kenneth K. Munson 2001-09-11
6233675 Facility to allow fast execution of and, or, and test instructions Kenneth K. Munson 2001-05-15