JN

John R. Nickolls

NV NVIDIA: 55 patents #56 of 7,811Top 1%
MC Maspar Computer: 6 patents #1 of 14Top 8%
Broadcom: 5 patents #2,110 of 9,346Top 25%
Overall (All Time): #32,985 of 4,157,543Top 1%
66
Patents All Time

Issued Patents All Time

Showing 25 most recent of 66 patents

Patent #TitleCo-InventorsDate
10365930 Instructions for managing a parallel cache hierarchy Brett W. Coon, Michael C. Shebanow 2019-07-30
10360039 Predicted instruction execution in parallel processors with reduced per-thread state information including choosing a minimum or maximum of two operands based on a predicate value Richard Craig Johnson, Robert Steven Glanville 2019-07-23
10152328 Systems and methods for voting among parallel threads Lars Nyland, Peter C. Mills, Jeremy Sugerman, Timothy Foley, Brian Fahs +2 more 2018-12-11
9952977 Cache operations and policies for a multi-threaded client Steven James Heinrich, Alexander L. Minkin, Brett W. Coon, Rajeshwaran Selvanesan, Robert Steven Glanville +4 more 2018-04-24
9830197 Cooperative thread array reduction and scan operations Brian Fahs, Ming Y. Siu, Brett W. Coon, Lars Nyland 2017-11-28
9639365 Indirect function call instructions in a synchronous parallel thread processor Brett W. Coon, Lars Nyland, Peter C. Mills, John Erik Lindholm 2017-05-02
9639479 Instructions for managing a parallel cache hierarchy Brett W. Coon, Michael C. Shebanow 2017-05-02
9519947 Architecture and instructions for accessing multi-dimensional formatted surface memory Brian Fahs, Lars Nyland, John Erik Lindholm, Richard Craig Johnson 2016-12-13
9417875 Cooperative thread array reduction and scan operations Brian Fahs, Ming Y. Siu, Brett W. Coon, Lars Nyland 2016-08-16
9286256 Sharing data crossbar for reads and writes in a data cache Alexander L. Minkin, Steven James Heinrich, Rajeshwaran Selvanesan, Stewart Glenn Carlton 2016-03-15
9223578 Coalescing memory barrier operations across multiple parallel threads Steven James Heinrich, Brett W. Coon, Michael C. Shebanow 2015-12-29
8751771 Efficient implementation of arrays of structures on SIMT and SIMD architectures Brian Fahs, Henry Packard Moreton, Brett W. Coon 2014-06-10
8732713 Thread group scheduler for computing on a parallel thread processor Brett W. Coon, John Erik Lindholm, Robert J. Stoll, Nicholas Wang, Jack Choquette 2014-05-20
8700877 Address mapping for a parallel thread processor Michael C. Shebanow, Yan Yan Tang 2014-04-15
8677106 Unanimous branch instructions in a parallel thread processor Richard Craig Johnson, Robert Steven Glanville, Guillermo J. Rozas 2014-03-18
8645638 Shared single-access memory with management of multiple parallel requests Brett W. Coon, Ming Y. Siu, Weizhong Xu, Stuart F. Oberman, Peter C. Mills 2014-02-04
8615646 Unanimous branch instructions in a parallel thread processor Richard Craig Johnson, Robert Steven Glanville, Guillermo J. Rozas 2013-12-24
8615541 Extended-precision integer arithmetic and logical instructions Richard Craig Johnson 2013-12-24
8539204 Cooperative thread array reduction and scan operations Brian Fahs, Ming Y. Siu, Brett W. Coon, Lars Nyland 2013-09-17
8522000 Trap handler architecture for a parallel processing unit Michael C. Shebanow, Jack Choquette, Brett W. Coon, Steven James Heinrich, Aravind Kalaiah +4 more 2013-08-27
8392669 Systems and methods for coalescing memory accesses of parallel threads Lars Nyland, Gentaro Hirota, Tanmoy Mandal 2013-03-05
8375176 Lock mechanism to enable atomic updates to shared memory Brett W. Coon, Lars Nyland, Peter C. Mills 2013-02-12
8321849 Virtual architecture and instruction set for parallel thread computing Henry Packard Moreton, Lars Nyland, Ian A. Buck, Richard Craig Johnson, Robert Steven Glanville +1 more 2012-11-27
8312254 Indirect function call instructions in a synchronous parallel thread processor Brett W. Coon, Lars Nyland, Peter C. Mills, John Erik Lindholm 2012-11-13
8271763 Unified addressing and instructions for accessing parallel memory spaces Brett W. Coon, Ian A. Buck, Robert Steven Glanville 2012-09-18