Issued Patents All Time
Showing 25 most recent of 126 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10983699 | Queue manager for streaming multiprocessor systems | — | 2021-04-20 |
| 10489056 | Queue manager for streaming multiprocessor systems | — | 2019-11-26 |
| 10346212 | Approach for a configurable phase-based priority scheduler | Jack Choquette, Olivier Giroux, Robert J. Stoll, Gary M. Tarolli | 2019-07-09 |
| 10242485 | Beam tracing | Tero Tapani Karras, Timo Oskari Aila, Samuli Matias Laine | 2019-03-26 |
| 10217184 | Programmable graphics processor for multithreaded execution of programs | Brett W. Coon, Stuart F. Oberman, Ming Y. Siu, Matthew P. Gerlach | 2019-02-26 |
| 9921847 | Tree-based thread management | — | 2018-03-20 |
| 9830161 | Tree-based thread management | Michael C. Shebanow | 2017-11-28 |
| 9659339 | Programmable graphics processor for multithreaded execution of programs | Brett W. Coon, Stuart F. Oberman, Ming Y. Siu, Matthew P. Gerlach | 2017-05-23 |
| 9639365 | Indirect function call instructions in a synchronous parallel thread processor | Brett W. Coon, John R. Nickolls, Lars Nyland, Peter C. Mills | 2017-05-02 |
| 9569559 | Beam tracing | Tero Tapani Karras, Timo Oskari Aila, Samuli Matias Laine | 2017-02-14 |
| 9519947 | Architecture and instructions for accessing multi-dimensional formatted surface memory | John R. Nickolls, Brian Fahs, Lars Nyland, Richard Craig Johnson | 2016-12-13 |
| 9448803 | System and method for hardware scheduling of conditional barriers and impatient barriers | Tero Tapani Karras, Timo Oskari Aila, Samuli Matias Laine | 2016-09-20 |
| 9442755 | System and method for hardware scheduling of indexed barriers | Tero Tapani Karras | 2016-09-13 |
| 9304775 | Dispatching of instructions for execution by heterogeneous processing engines | Jered Wierzbicki | 2016-04-05 |
| 9195460 | Using condition codes in the presence of non-numeric values | Robert Steven Glanville, Ming Y. Siu | 2015-11-24 |
| 9189242 | Credit-based streaming multiprocessor warp scheduling | Brett W. Coon, Jered Wierzbicki, Robert J. Stoll, Stuart F. Oberman | 2015-11-17 |
| 9171525 | Graphics processing unit with a texture return buffer and a texture queue | — | 2015-10-27 |
| 9158595 | Hardware scheduling of ordered critical code sections | Tero Tapani Karras, Samuli Matias Laine, Timo Oskari Aila | 2015-10-13 |
| 9058672 | Using a pixel offset for evaluating a plane equation | Henry Packard Moreton, Ming Y. Siu, Stuart F. Oberman | 2015-06-16 |
| 8976195 | Generating clip state for a batch of vertices | Ziyad S. Hakura | 2015-03-10 |
| 8949841 | Approach for a configurable phase-based priority scheduler | Jack Choquette, Olivier Giroux, Robert J. Stoll, Gary M. Tarolli | 2015-02-03 |
| 8860737 | Programmable graphics processor for multithreaded execution of programs | Brett W. Coon, Stuart F. Oberman, Ming Y. Siu, Matthew P. Gerlach | 2014-10-14 |
| 8730252 | System, method and computer program product for bump mapping | Henry Packard Moreton, Matthew Nicholas Papakipos, Harold Robert Feldman Zatz | 2014-05-20 |
| 8730249 | Parallel array architecture for a graphics processor | John M. Danskin, John S. Montrym, Steven E. Molnar, Mark J. French | 2014-05-20 |
| 8732711 | Two-level scheduler for multi-threaded processing | William J. Dally, Stephen W. Keckler, David Tarjan, Mark Alan Gebhart, Daniel R. Johnson | 2014-05-20 |