Issued Patents All Time
Showing 51–66 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7477091 | Defect tolerant redundancy | — | 2009-01-13 |
| 7456835 | Register based queuing for texture requests | John Erik Lindholm, Simon Moy, Brett W. Coon | 2008-11-25 |
| 7403964 | Galois field multiplier array for use within a finite field arithmetic unit | Joshua Porten, Won Kim, Scott Johnson | 2008-07-22 |
| 7343472 | Processor having a finite field arithmetic unit utilizing an array of multipliers and adders | Joshua Porten, Won Kim, Scott Johnson | 2008-03-11 |
| 7339592 | Simulating multiported memories using lower port count memories | John Erik Lindholm, Ming Y. Siu, Simon Moy, Samuel Liu | 2008-03-04 |
| 7313583 | Galois field arithmetic unit for use within a processor | Joshua Porten, Won Kim, Scott Johnson | 2007-12-25 |
| 7027062 | Register based queuing for texture requests | John Erik Lindholm, Simon Moy, Brett W. Coon | 2006-04-11 |
| 6976141 | Pipelined multi-access memory apparatus and method | Lawrence J. Madar, III, Ethan Mirsky | 2005-12-13 |
| 6959378 | Reconfigurable processing system and method | Scott Johnson, Mark Williams, Ethan Mirsky, Kambdur Kirthiranjan, Amrit Pant +1 more | 2005-10-25 |
| 6879207 | Defect tolerant redundancy | — | 2005-04-12 |
| 5598408 | Scalable processor to processor and processor to I/O interconnection network and method for parallel processing arrays | John Zapisek, Won Kim, Jeffrey C. Kalb, Jr., W. Thomas Blank, Eliot Leonard Wegbreit +1 more | 1997-01-28 |
| 5581777 | Parallel processor memory transfer system using parallel transfers between processors and staging registers and sequential transfers between staging registers and memory | Won Kim, David M. Bulfer, W. Thomas Blank, Hannes Figel | 1996-12-03 |
| 5542074 | Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount | Won Kim | 1996-07-30 |
| 5488694 | Broadcasting headers to configure physical devices interfacing a data bus with a logical assignment and to effect block data transfers between the configured logical devices | Mark McKee, John Zapisek, David M. Bulfer, John M. Long, William Thomas Blank | 1996-01-30 |
| 5280474 | Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays | John Zapisek, Won Kim, Jeffery C. Kalb, W. Thomas Blank, Eliot Leonard Wegbreit +1 more | 1994-01-18 |
| 5243699 | Input/output system for parallel processing arrays | Won Kim, John Zapisek, William Thomas Blank | 1993-09-07 |