IJ

Ihab Jaser

M( Microsemi Storage Solutions (U.S.): 4 patents #7 of 64Top 15%
PM Pmc-Sierra: 4 patents #124 of 275Top 50%
WH Whittaker: 3 patents #2 of 52Top 4%
MI Microchip Technology Incorporated: 2 patents #307 of 958Top 35%
Overall (All Time): #329,862 of 4,157,543Top 8%
14
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12197320 System and method for enhancing flash channel utilization Nima Nikuie, Jack Wynne 2025-01-14
11914899 System for managing access to a memory resource by multiple users Kwok Kong, William Brent Wilson, Donia Sebastian, Dan R. McLeran 2024-02-27
9590656 System and method for higher quality log likelihood ratios in LDPC decoding Rino Micheloni, Alessia Marelli, Peter Z. Onufryk, Christopher I. W. Norrie, Luca Crippa 2017-03-07
9477562 Apparatus and method for minimizing exclusive-OR (XOR) computation time Mohammad Seyed Nikuie 2016-10-25
9454414 System and method for accumulating soft information in LDPC decoding Rino Micheloni, Alessia Marelli, Peter Z. Onufryk, Christopher I. W. Norrie, Luca Crippa 2016-09-27
9448881 Memory controller and integrated circuit device for correcting errors in data read from memory cells Rino Micheloni, Alessia Marelli, Peter Z. Onufryk, Christopher I. W. Norrie 2016-09-20
9128858 Apparatus and method for adjusting a correctable raw bit error rate limit in a memory system using strong log-likelihood (LLR) values Rino Micheloni, Peter Z. Onufryk, Alessia Marelli, Christopher I. W. Norrie 2015-09-08
9092353 Apparatus and method based on LDPC codes for adjusting a correctable raw bit error rate limit in a memory system Rino Micheloni, Peter Z. Onufryk, Alessia Marelli, Christopher I. W. Norrie 2015-07-28
8588228 Nonvolatile memory controller with host controller interface for retrieving and dispatching nonvolatile memory commands in a distributed manner Peter Z. Onufryk, Jayesh Patel, Ganesh T. Seshan 2013-11-19
8554968 Interrupt technique for a nonvolatile memory controller Peter Z. Onufryk, Jayesh Patel 2013-10-08
6141323 Closed loop congestion control using a queue measurement system Marinica Rusu 2000-10-31
6137807 Dual bank queue memory and queue control system Marinica Rusu 2000-10-24
6111880 Hybrid packet/cell switching, linking, and control system and methodology for sharing a common internal cell format Marinica Rusu 2000-08-29
5938749 Queue measurement apparatus and methodology Marinica Rusu 1999-08-17