Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11367707 | Semiconductor package or structure with dual-sided interposers and memory | Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan | 2022-06-21 |
| 11336559 | Fast-lane routing for multi-chip packages | Adel A. Elsherbini, Tejpal Singh, Shawna M. Liff, Johanna M. Swan | 2022-05-17 |
| 11294852 | Multiple dies hardware processors and methods | Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Siva Soumya Eachempati, Tejpal Singh +10 more | 2022-04-05 |
| 11270947 | Composite interposer structure and method of providing same | Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan | 2022-03-08 |
| 11205630 | Vias in composite IC chip structures | Adel A. Elsherbini, Patrick Morrow, Johanna M. Swan, Shawna M. Liff, Mauro Kobrinksy +1 more | 2021-12-21 |
| 11094672 | Composite IC chips including a chiplet embedded within metallization layers of a host IC chip | Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Patrick Morrow, Van H. Le | 2021-08-17 |
| 11003610 | Multichip package link | Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Ananthan Ayyasamy, Xiaobel Li +2 more | 2021-05-11 |
| 10998302 | Packaged device with a chiplet comprising memory resources | Adel A. Elsherbini, Van H. Le, Johanna M. Swan, Shawna M. Liff, Patrick Morrow +1 more | 2021-05-04 |
| 10854548 | Inter-die passive interconnects approaching monolithic performance | Zuoguo Wu, Debendra Das Sharma, Adel A. Elsherbini | 2020-12-01 |
| 10795853 | Multiple dies hardware processors and methods | Nevine Nassif, Yen-Cheng Liu, Krishnakanth V. Sistla, Siva Soumya Eachempati, Tejpal Singh +10 more | 2020-10-06 |
| 10686582 | Clock phase compensation apparatus and method | Nasser A. Kurd, Peipei Wang, Yingyu Miao, Lakshmipriya Seshan, Ishaan S. Shah | 2020-06-16 |
| 10560081 | Method, apparatus, system for centering in a high performance interconnect | Mahesh Wagh, Zuoguo Wu, Venkatraman Iyer, Todd Hinck, David M. Lee +1 more | 2020-02-11 |
| 10552357 | Multichip package link | Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Ananthan Ayyasamy, Xiaobei Li +2 more | 2020-02-04 |
| 10461805 | Valid lane training | Venkatraman Iyer, Lip Khoon Teh, Mahesh Wagh, Zuoguo Wu, Azydee Hamid | 2019-10-29 |
| 10073808 | Multichip package link | Zuoguo Wu, Mahesh Wagh, Debendra Das Sharma, Ananthan Ayyasamy, Xiaobei Li +2 more | 2018-09-11 |
| 9946676 | Multichip package link | Mahesh Wagh, Zuoguo Wu, Venkatraman Iyer, Mark S. Birrittella, Ishwar Agarwal +3 more | 2018-04-17 |
| 9692402 | Method, apparatus, system for centering in a high performance interconnect | Mahesh Wagh, Zuoguo Wu, Venkatraman Iyer, Todd Hinck, David M. Lee +1 more | 2017-06-27 |
| 6326802 | On-die adaptive arrangements for continuous process, voltage and temperature compensation | Paul F. Newman, Jeff Jones, Greg Taylor, Chee Bow Lim | 2001-12-04 |