Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
AE

Adel A. Elsherbini — 270 Patents

Intel: 268 patents #27 of 30,777Top 1%
SHSanta Clara Holdings: 1 patents #1 of 24Top 5%
TRTahoe Research: 1 patents #81 of 215Top 40%
Chandler, AZ: #2 of 3,331 inventorsTop 1%
Arizona: #19 of 32,909 inventorsTop 1%
Overall (All Time): #1,672 of 4,157,543Top 1%
270 Patents All Time
Adel A. Elsherbini has been granted 270 US patents while listed as an inventor at Intel. The first was granted in 2015 and the most recent in December 2025. Adel A. Elsherbini ranks #1,672 of 4,157,543 US inventors in our database (top 0.04%). Patent records list Adel A. Elsherbini in Chandler, AZ, US.

Issued Patents All Time

Showing 1–25 of 270 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12500207 Packaging architecture with intermediate routing layers Kimin Jun, Christopher M. Pelto, Georgios Dogiamis, Bradley A. Jackson, Shawna M. Liff +1 more 2025-12-16
12500177 Microelectronic assemblies with communication networks Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan 2025-12-16
12487420 Apparatus and method of manufacturing a vertically disaggregated photonic device Henning Braunisch 2025-12-02
12489032 Cooling of conformal power delivery structures Feras Eid, Aleksandar Aleksov, Henning Braunisch, Thomas L. Sounart, Johanna M. Swan 2025-12-02
12469630 Inductor and transformer semiconductor devices using hybrid bonding technology Georgios Dogiamis, Qiang Yu, Kimin Jun 2025-11-11
12469820 Fine-grained disaggregated server architecture Carleton L. Molnar, Tanay Karnik, Shawna M. Liff, Robert J. Munoz, Julien Sebot +6 more 2025-11-11
12463156 Packaging architectures for sub-terahertz radio frequency devices Georgios Dogiamis 2025-11-04
12456702 Device, method and system to mitigate stress on hybrid bonds in a multi-tier arrangement of chiplets Kimin Jun, Feras Eid, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan +1 more 2025-10-28
12438087 High throughput additive manufacturing for integrated circuit components containing traces with feature size and grain boundaries Aleksandar Aleksov, Feras Eid, Weiyi Li, Stephen L. Morein, Yoshihiro Tomita 2025-10-07
12431430 Technologies for high throughput additive manufacturing for integrated circuit components Yoshihiro Tomita, Aleksandar Aleksov, Feras Eid, Wenhao Li, Stephen L. Morein 2025-09-30
12424589 Contiguous shield structures in microelectronic assemblies having hybrid bonding Beomseok Choi, Han Wui Then, Johanna M. Swan, Shawna M. Liff 2025-09-23
12424543 Selective interconnects in back-end-of-line metallization stacks of integrated circuitry Shawna M. Liff, Johanna M. Swan 2025-09-23
12417978 Microelectronic assemblies having backside die-to-package interconnects Kimin Jun, Shawna M. Liff, Johanna M. Swan, Han Wui Then 2025-09-16
12412881 Microelectronic assemblies Shawna M. Liff, Johanna M. Swan, Arun Chandrasekhar 2025-09-09
12406962 Power delivery through capacitor-dies in a multi-layered microelectronic assembly William J. Lambert, Krishna Bharath, Shawna M. Liff, Nicolas Butzen, Georgios Dogiamis +4 more 2025-09-02
12381182 Direct bonding in microelectronic assemblies Feras Eid, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan 2025-08-05
12362297 Semiconductor packages with antennas Telesphor Kamgaing, Sasha N. Oster 2025-07-15
12362284 Composite interposer structure and method of providing same Shawna M. Liff, Johanna M. Swan, Gerald Pasdast 2025-07-15
12341114 Microelectronic assemblies having a hybrid bonded interposer for die-to-die fan-out scaling Georgios Dogiamis, Qiang Yu, Shawna M. Liff 2025-06-24
12327827 Microelectronic assemblies Shawna M. Liff, Johanna M. Swan, Arun Chandrasekhar 2025-06-10
12327775 Thermal performance in hybrid bonded 3D die stacks Feras Eid, Johanna M. Swan, Shawna M. Liff, Aleksandar Aleksov, Julien Sebot 2025-06-10
12315840 Microelectronic assemblies Shawna M. Liff, Johanna M. Swan 2025-05-27
12315794 Skip level vias in metallization layers for integrated circuit devices Mauro J. Kobrinsky, Shawna M. Liff, Johanna M. Swan, Gerald Pasdast, Sathya Narasimman Tiagaraj 2025-05-27
12308362 Packaging architecture for disaggregated integrated voltage regulators Kaladhar Radhakrishnan, Krishna Bharath, William J. Lambert, Sriram Srinivasan, Christopher Schaef 2025-05-20
12300666 Microelectronic assemblies with communication networks Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan 2025-05-13