Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10491472 | Coordinating width changes for an active network link | Brent R. Rothermel | 2019-11-26 |
| 10372647 | Exascale fabric time synchronization | Thomas D. Lovett, Michael A. Parker | 2019-08-06 |
| 10305802 | Reliable transport of ethernet packet data with wire-speed and packet data rate match | Thomas D. Lovett, Todd Rimmer | 2019-05-28 |
| 10230665 | Hierarchical/lossless packet preemption to reduce latency jitter in flow-controlled packet-based networks | Thomas D. Lovett, Albert Cheng, James A. Kunz, Todd Rimmer | 2019-03-12 |
| 9946676 | Multichip package link | Mahesh Wagh, Zuoguo Wu, Venkatraman Iyer, Gerald Pasdast, Ishwar Agarwal +3 more | 2018-04-17 |
| 9887804 | Lane error detection and lane removal mechanism to reduce the probability of data corruption | — | 2018-02-06 |
| 9819452 | Efficient link layer retry protocol utilizing implicit acknowledgements | — | 2017-11-14 |
| 9628382 | Reliable transport of ethernet packet data with wire-speed and packet data rate match | Thomas D. Lovett, Todd Rimmer | 2017-04-18 |
| 9397792 | Efficient link layer retry protocol utilizing implicit acknowledgements | — | 2016-07-19 |
| 9325449 | Lane error detection and lane removal mechanism to reduce the probability of data corruption | — | 2016-04-26 |
| 9306863 | Link transfer, bit error detection and link retry using flit bundles asynchronous to link fabric packets | — | 2016-04-05 |
| 7587305 | Transistor level verilog | Robert James Lutz, Eric C. Fromm, Harro Zimmermann | 2009-09-08 |
| 6992515 | Clock signal duty cycle adjust circuit | — | 2006-01-31 |
| 6836153 | Systems and methods for phase detector circuit with reduced offset | — | 2004-12-28 |
| 6775339 | Circuit design for high-speed digital communication | Paul Wildes | 2004-08-10 |
| 6266759 | Register scoreboarding to support overlapped execution of vector memory reference instructions in a vector processor | — | 2001-07-24 |
| 5797035 | Networked multiprocessor system with global distributed memory and block transfer engine | Richard E. Kessler, Steven M. Oberlin, Randal S. Passint, Greg Thorson | 1998-08-18 |
| 5737628 | Multiprocessor computer system with interleaved processing element nodes | Richard E. Kessler, Steven M. Oberlin, Randal S. Passint, Greg Thorson | 1998-04-07 |
| 5583990 | System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channel | Richard E. Kessler, Steven M. Oberlin, Randal S. Passint, Greg Thorson | 1996-12-10 |
| 5182473 | Emitter emitter logic (EEL) and emitter collector dotted logic (ECDL) families | Jan Wikström, David R. Kiefer, Stephen B. Smetana, Vernon W. Swanson | 1993-01-26 |
| 5177380 | ECL latch with single-ended and differential inputs | — | 1993-01-05 |
| 4964081 | READ-WHILE-WRITE RAM CELL | Jan Wikström | 1990-10-16 |
| 4717677 | Fabricating a semiconductor device with buried oxide | Kevin L. McLaughlin | 1988-01-05 |
| 4701882 | Bipolar RAM cell | James J. Stipanuk | 1987-10-20 |
| 4697251 | Bipolar RAM cell | James J. Stipanuk | 1987-09-29 |