Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10725919 | Processors having virtually clustered cores and cache slices | Herbert Hum, Brinda Ganesh, James Vash, Ganesh Kumar, Leena K. Puthiyedath +6 more | 2020-07-28 |
| 10725920 | Processors having virtually clustered cores and cache slices | Herbert Hum, Brinda Ganesh, James Vash, Ganesh Kumar, Leena K. Puthiyedath +6 more | 2020-07-28 |
| 10705960 | Processors having virtually clustered cores and cache slices | Herbert Hum, Brinda Ganesh, James Vash, Ganesh Kumar, Leena K. Puthiyedath +6 more | 2020-07-07 |
| 10073779 | Processors having virtually clustered cores and cache slices | Herbert Hum, Brinda Ganesh, James Vash, Ganesh Kumar, Leena K. Puthiyedath +6 more | 2018-09-11 |
| 9798556 | Method, system, and apparatus for dynamic reconfiguration of resources | Mani Ayyar, Ioannis Schoinas, Akhilesh Kumar, Doddaballapur N. Jayasimha, Jose A. Vargas | 2017-10-24 |
| 9792212 | Virtual shared cache mechanism in a processing device | Yen-Cheng Liu, Aamer Jaleel, Bongjin Jung, Zeshan A. Chishti, Adrian C. Moga +1 more | 2017-10-17 |
| 9223738 | Method, system, and apparatus for dynamic reconfiguration of resources | Mani Ayyar, Ioannis Schoinas, Akhilesh Kumar, Doddaballapur N. Jayasimha, Jose A. Vargas | 2015-12-29 |
| 9183144 | Power gating a portion of a cache memory | Ren Wang, Ahmad Samih, Pinkesh Shah, Zeshan A. Chishti, Christian Maciocco +1 more | 2015-11-10 |
| 9176875 | Power gating a portion of a cache memory | Ren Wang, Ahmad Samih, Pinkesh Shah, Zeshan A. Chishti, Christian Maciocco +1 more | 2015-11-03 |
| 8799586 | Memory mirroring and migration at home agent | Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Gregory S. Averill | 2014-08-05 |
| 8782347 | Controllably exiting an unknown state of a cache coherency directory | Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Gregory S. Averill | 2014-07-15 |
| 8327113 | Method, system, and apparatus for dynamic reconfiguration of resources | Mani Ayyar, Ioannis T. Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose A. Vargas | 2012-12-04 |
| 8327228 | Home agent data and memory management | Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Gregory S. Averill | 2012-12-04 |
| 8219780 | Mitigating context switch cache miss penalty | James Callister, Rohit Bhatia, Shawn Walker, Mark Gibson | 2012-07-10 |
| 8171121 | Method, system, and apparatus for dynamic reconfiguration of resources | Mani Ayyar, Ioannis T. Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose A. Vargas | 2012-05-01 |
| 7930539 | Computer system resource access control | Donald Soltis, Rohit Bhatia | 2011-04-19 |
| 7734741 | Method, system, and apparatus for dynamic reconfiguration of resources | Mani Ayyar, Ioannis T. Schoinas, Akhilesh Kumar, Jay Jayasimha, Jose A. Vargas | 2010-06-08 |
| 7451260 | Interleave mechanism for a computing environment | Christopher L. Lyles | 2008-11-11 |
| 7421689 | Processor-architecture for facilitating a virtual machine monitor | Jonathan Ross, Dale Morris, Donald Soltis, Rohit Bhatia | 2008-09-02 |
| 7398374 | Multi-cluster processor for processing instructions of one or more instruction threads | — | 2008-07-08 |
| 7370135 | Band configuration agent for link based computing system | Ioannis Schoinas, Akhilesh Kumar, Doddaballapur N. Jayasimha | 2008-05-06 |
| 7310751 | Timeout event trigger generation | Michael Tayler | 2007-12-18 |
| 7296181 | Lockstep error signaling | Kevin Safford | 2007-11-13 |
| 7290169 | Core-level processor lockstepping | Kevin Safford, Christopher L. Lyles | 2007-10-30 |
| 7237144 | Off-chip lockstep checking | Kevin Safford, Donald Soltis | 2007-06-26 |