Issued Patents All Time
Showing 26–41 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7028167 | Core parallel execution with different optimization characteristics to decrease dynamic execution path | Donald Soltis | 2006-04-11 |
| 6941489 | Checkpointing of register file | — | 2005-09-06 |
| 6931489 | Apparatus and methods for sharing cache among processors | Samuel D. Naffziger | 2005-08-16 |
| 6895497 | Multidispatch CPU integrated circuit having virtualized and modular resources and adjustable dispatch priority | Eric Fetzer, Wayne Kever | 2005-05-17 |
| 6820167 | Configurable crossbar and related methods | Samuel D. Naffziger | 2004-11-16 |
| 6427188 | Method and system for early tag accesses for lower-level caches in parallel with first-level cache | Terry L Lyon, Dean Mulla | 2002-07-30 |
| 6049851 | Method and apparatus for checking cache coherency in a computer architecture | William R. Bryg, Kenneth K. Chan, John F. Shelton | 2000-04-11 |
| 5787494 | Software assisted hardware TLB miss handler | Michael Buckley, Duncan C. Weir | 1998-07-28 |
| 5617549 | System and method for selecting and buffering even and odd instructions for simultaneous execution in a computer | — | 1997-04-01 |
| 5603004 | Method for decreasing time penalty resulting from a cache miss in a multi-level cache system | Gordon Kurpanek, Michael Buckley, William R. Bryg | 1997-02-11 |
| 5526500 | System for operand bypassing to allow a one and one-half cycle cache memory access time for sequential load and branch instructions | Darius Tanksalvala, Patrick Knebel, Thomas R. Hotchkiss, R. Craig Simpson | 1996-06-11 |
| 5493660 | Software assisted hardware TLB miss handler | Michael Buckley, Duncan C. Weir | 1996-02-20 |
| 5471602 | System and method of scoreboarding individual cache line segments | — | 1995-11-28 |
| 5404496 | Computer-based system and method for debugging a computer system implementation | Gregory D. Burroughs, Steven W. LaMar | 1995-04-04 |
| 5396604 | System and method for reducing the penalty associated with data cache misses | Mark A. Forsyth | 1995-03-07 |
| 5337415 | Predecoding instructions for supercalar dependency indicating simultaneous execution for increased operating frequency | Craig A. Gleason, Mark A. Forsyth | 1994-08-09 |