Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6021500 | Processor with sleep and deep sleep modes | Tsan-Kuen Wang, Samson Huang, Edward T. Grochowski | 2000-02-01 |
| 6014720 | Dynamically sizing a bus transaction for dual bus size interoperability based on bus transaction signals | Tsan-Kuen Wang | 2000-01-11 |
| 5948099 | Apparatus and method for swapping the byte order of a data item to effectuate memory format conversion | John H. Crawford | 1999-09-07 |
| 5895489 | Memory management system including an inclusion bit for maintaining cache coherency | Gary N. Hammond, Pradeep Kumar Dubey | 1999-04-20 |
| 5768558 | Identification of the distinction between the beginning of a new write back cycle and an ongoing write cycle | Sundaravarathan R. Iyengar | 1998-06-16 |
| 5699548 | Method and apparatus for selecting a mode for updating external memory | Sundaravarathan R. Iyengar, Tsan-Kuen Wang, Murali S. Talwai, James F. McKevitt, III | 1997-12-16 |
| 5696935 | Multiported cache and systems | Edward T. Grochowski | 1997-12-09 |
| 5669014 | System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width | Sundaravarathan R. Iyengar | 1997-09-16 |
| 5559986 | Interleaved cache for multiple accesses per clock cycle in a microprocessor | Donald B. Alpert, Jack Mills | 1996-09-24 |