Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8904205 | Increasing power efficiency of turbo mode operation in a processor | James S. Burns, Baskaran Ganesan, Russell J. Fenger, Devadatta V. Bodas, Feranak Nelson +2 more | 2014-12-02 |
| 8862918 | Efficient frequency boost operation | Baskaran Ganesan, James S. Burns, Suresh Sugumar, Devadatta V. Bodas, Feranak Nelson +2 more | 2014-10-14 |
| 8793515 | Increasing power efficiency of turbo mode operation in a processor | James S. Burns, Baskaran Ganesan, Russell J. Fenger, Devadatta V. Bodas, Feranak Nelson +2 more | 2014-07-29 |
| 8683240 | Increasing power efficiency of turbo mode operation in a processor | James S. Burns, Baskaran Ganesan, Russell J. Fenger, Devadatta V. Bodas, Feranak Nelson +2 more | 2014-03-25 |
| 5768558 | Identification of the distinction between the beginning of a new write back cycle and an ongoing write cycle | Mustafiz R. Choudhury | 1998-06-16 |
| 5724547 | LRU pointer updating in a controller for two-way set associative cache | James Nadir | 1998-03-03 |
| 5699548 | Method and apparatus for selecting a mode for updating external memory | Mustafiz R. Choudhury, Tsan-Kuen Wang, Murali S. Talwai, James F. McKevitt, III | 1997-12-16 |
| 5669014 | System and method having processor with selectable burst or no-burst write back mode depending upon signal indicating the system is configured to accept bit width larger than the bus width | Mustafiz R. Choudhury | 1997-09-16 |
| 5530833 | Apparatus and method for updating LRU pointer in a controller for two-way set associative cache | James Nadir | 1996-06-25 |
| 5392417 | Processor cycle tracking in a controller for two-way set associative cache | James Nadir | 1995-02-21 |
| 5367659 | Tag initialization in a controller for two-way set associative cache | James Nadir | 1994-11-22 |
| 5210845 | Controller for two-way set associative cache | John H. Crawford, James Nadir | 1993-05-11 |