Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10921018 | Self-sealing vent assembly | Sashrik Sribhashyam | 2021-02-16 |
| 5737569 | Multiport high speed memory having contention arbitration capability without standby delay | Ching-Hua Chu | 1998-04-07 |
| 5724547 | LRU pointer updating in a controller for two-way set associative cache | Sundaravarathan R. Iyengar | 1998-03-03 |
| 5530833 | Apparatus and method for updating LRU pointer in a controller for two-way set associative cache | Sundaravarathan R. Iyengar | 1996-06-25 |
| 5517136 | Opportunistic time-borrowing domino logic | David L. Harris, Sunny C. Huang, Ching-Hua Chu, Jason Stinson, Alper Ilkbahar | 1996-05-14 |
| 5479641 | Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking | Ching-Hua Chu | 1995-12-26 |
| 5450565 | Circuit and method for selecting a set in a set associative cache | Ching-Hua Chu | 1995-09-12 |
| 5392417 | Processor cycle tracking in a controller for two-way set associative cache | Sundaravarathan R. Iyengar | 1995-02-21 |
| 5367659 | Tag initialization in a controller for two-way set associative cache | Sundaravarathan R. Iyengar | 1994-11-22 |
| 5339399 | Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus | Yong-Fong Lee, Nagraj Palasamudram | 1994-08-16 |
| 5210845 | Controller for two-way set associative cache | John H. Crawford, Sundaravarathan R. Iyengar | 1993-05-11 |
| 4257095 | System bus arbitration, circuitry and methodology | — | 1981-03-17 |