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USPTO Patent Rankings Data through Dec 31, 2025
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James Nadir — 12 Patents

Intel: 11 patents #3,726 of 30,777Top 15%
Sunnyvale, CA: #2,336 of 14,302 inventorsTop 20%
California: #51,404 of 386,348 inventorsTop 15%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
James Nadir has been granted 12 US patents while listed as an inventor at Intel. The first was granted in 1981 and the most recent in February 2021. James Nadir ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list James Nadir in Sunnyvale, CA, US.

Patents per Year

Patents granted per year, 1981 to 2021Bar chart with a peak of 3 patents in 1995.peak 31981: 1 patents19811993: 1 patents19931994: 2 patents19941995: 3 patents19951996: 2 patents19961998: 2 patents19982021: 1 patents2021

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10921018 Self-sealing vent assembly Sashrik Sribhashyam 2021-02-16
5737569 Multiport high speed memory having contention arbitration capability without standby delay Ching-Hua Chu 1998-04-07 $69,264,000
5724547 LRU pointer updating in a controller for two-way set associative cache Sundaravarathan R. Iyengar 1998-03-03 $75,970,000
5530833 Apparatus and method for updating LRU pointer in a controller for two-way set associative cache Sundaravarathan R. Iyengar 1996-06-25 $66,281,000
5517136 Opportunistic time-borrowing domino logic David L. Harris, Sunny C. Huang, Ching-Hua Chu, Jason Stinson, Alper Ilkbahar 1996-05-14 $73,336,000
5479641 Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking Ching-Hua Chu 1995-12-26 $51,594,000
5450565 Circuit and method for selecting a set in a set associative cache Ching-Hua Chu 1995-09-12 $62,521,000
5392417 Processor cycle tracking in a controller for two-way set associative cache Sundaravarathan R. Iyengar 1995-02-21 $27,658,000
5367659 Tag initialization in a controller for two-way set associative cache Sundaravarathan R. Iyengar 1994-11-22 $19,549,000
5339399 Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus Yong-Fong Lee, Nagraj Palasamudram 1994-08-16 $31,670,000
5210845 Controller for two-way set associative cache John H. Crawford, Sundaravarathan R. Iyengar 1993-05-11 $171,882,000
4257095 System bus arbitration, circuitry and methodology 1981-03-17 $11,082,000