Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10802070 | Testing device and testing method with spike protection | Cheng-Hsien Chang | 2020-10-13 |
| 9978604 | Salicide formation using a cap layer | Mei-Hsuan Lin, Chih-Hsun Lin, Ling-Sung Wang | 2018-05-22 |
| 9841487 | Calibration board for calibrating signal delays of test channels in an automatic test equipment and timing calibration method thereof | Hou-Chun CHEN, Shin-Wen Lin, Po-Kai Cheng | 2017-12-12 |
| 9842774 | Through substrate via structure for noise reduction | Chun-Lin FANG, Ping-Hao Lin, Hsiao-Chun Lee, Chi-Feng Huang | 2017-12-12 |
| 9647650 | Clock generating device | Cheng-Hsien Chang, Shin-Wen Lin | 2017-05-09 |
| 9343318 | Salicide formation using a cap layer | Mei-Hsuan Lin, Chih-Hsun Lin, Ling-Sung Wang | 2016-05-17 |
| 9209270 | MOS devices having non-uniform stressor doping | Mei-Hsuan Lin, Chih-Hsun Lin, Ling-Sung Wang | 2015-12-08 |
| 8994097 | MOS devices having non-uniform stressor doping | Mei-Hsuan Lin, Chih-Hsun Lin, Ling-Sung Wang | 2015-03-31 |
| 5737569 | Multiport high speed memory having contention arbitration capability without standby delay | James Nadir | 1998-04-07 |
| 5517136 | Opportunistic time-borrowing domino logic | David L. Harris, Sunny C. Huang, James Nadir, Jason Stinson, Alper Ilkbahar | 1996-05-14 |
| 5479641 | Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking | James Nadir | 1995-12-26 |
| 5450565 | Circuit and method for selecting a set in a set associative cache | James Nadir | 1995-09-12 |