Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12356684 | Semiconductor structure having asymmetric source/drain regions | HSING-I TSAI, Fu-Huan Tsai, Chia-Chung Chen, Chi-Feng Huang, Cho-Ying Lu +1 more | 2025-07-08 |
| 11855145 | Semiconductor structure | HSING-I TSAI, Fu-Huan Tsai, Chia-Chung Chen, Chi-Feng Huang, Cho-Ying Lu +1 more | 2023-12-26 |
| 10020251 | Semiconductor device and method fabricating the same | Chi-Feng Huang, Victor Chiang Liang | 2018-07-10 |
| 9842774 | Through substrate via structure for noise reduction | Chun-Lin FANG, Ping-Hao Lin, Ching-Hua Chu, Chi-Feng Huang | 2017-12-12 |
| 9780089 | Bipolar junction transistor layout | Han-Min Tsai, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Shou-Chun Chou +1 more | 2017-10-03 |
| 9768112 | Semiconductor device and method fabricating the same | Chi-Feng Huang, Victor Chiang Liang | 2017-09-19 |
| 9705466 | Semiconductor device with guard ring coupled resonant circuit | Yen-Jen Chen, Chi-Feng Huang, Hsieh-Hung Hsieh, Tzu-Jin Yeh | 2017-07-11 |
| 9484408 | Bipolar junction transistor layout | Han-Min Tsai, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Shou-Chun Chou +1 more | 2016-11-01 |
| 9406626 | Semiconductor device and method fabricating the same | Chi-Feng Huang, Victor Chiang Liang | 2016-08-02 |
| 8921978 | Dual DNW isolation structure for reducing RF noise on high voltage semiconductor devices | Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang | 2014-12-30 |