Issued Patents All Time
Showing 25 most recent of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10102886 | Techniques for probabilistic dynamic random access memory row repair | Brian S. Morris, Sreenivas Mandava, Raj K. Ramanujan | 2018-10-16 |
| 9934143 | Mapping a physical address differently to different memory devices in a group | Kuljit S. Bains, Suneeta Sah, Brian S. Morris | 2018-04-03 |
| 9910604 | Refresh parameter-dependent memory refresh management | Suneeta Sah | 2018-03-06 |
| 9857858 | Managing power consumption and performance of computing systems | Devadatta V. Bodas, Alan Gara | 2018-01-02 |
| 9824754 | Techniques for determining victim row addresses in a volatile memory | Sreenivas Mandava, Brian S. Morris, Suneeta Sah, Roy M. Stevens, Ted Rossin +1 more | 2017-11-21 |
| 9778720 | PCIE device power state control | Anil Kumar, Paul S. Diefenbaugh | 2017-10-03 |
| 9524009 | Managing the operation of a computing device by determining performance-power states | Devadatta V. Bodas | 2016-12-20 |
| 9449671 | Techniques for probabilistic dynamic random access memory row repair | Brian S. Morris, Sreenivas Mandava, Raj K. Ramanujan | 2016-09-20 |
| 9405595 | Synchronizing multiple threads efficiently | Sailesh Kottapalli | 2016-08-02 |
| 9269417 | Memory refresh management | Suneeta Sah | 2016-02-23 |
| 9269436 | Techniques for determining victim row addresses in a volatile memory | Sreenivas Mandava, Brian S. Morris, Suneeta Sah, Roy M. Stevens, Ted Rossin +1 more | 2016-02-23 |
| 9213390 | Periodic activity alignment | Eugene Gorbatov, Paul S. Diefenbaugh, Anil Kumar, Richard J. Greco | 2015-12-15 |
| 8887171 | Mechanisms to avoid inefficient core hopping and provide hardware assisted low-power state selection | Justin J. Song | 2014-11-11 |
| 8819684 | Synchronizing multiple threads efficiently | Sailesh Kottapalli | 2014-08-26 |
| 8473963 | Synchronizing multiple threads efficiently | Sailesh Kottapalli | 2013-06-25 |
| 8458412 | Transaction based shared data operations in a multiprocessor environment | Sailesh Kottapalli, Kushagra Vaid | 2013-06-04 |
| 8176266 | Transaction based shared data operations in a multiprocessor environment | Sailesh Kottapalli, Kushagra Vaid | 2012-05-08 |
| 7984248 | Transaction based shared data operations in a multiprocessor environment | Sailesh Kottapalli, Kushagra Vaid | 2011-07-19 |
| 7937709 | Synchronizing multiple threads efficiently | Sailesh Kottapalli | 2011-05-03 |
| 7877666 | Tracking health of integrated circuit structures | Tsvika Kurts, Moty Mehalel | 2011-01-25 |
| 7669009 | Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive caches | Sailesh Kottapalli | 2010-02-23 |
| 7607048 | Method and apparatus for protecting TLB's VPN from soft errors | Ugonna Echeruo, George Z. Chrysos, Shubhendu Sekhar Mukherjee | 2009-10-20 |
| 7395304 | Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic | Bharat Bhushan, Vinod Sharma, Edward T. Grochowski | 2008-07-01 |
| 7395415 | Method and apparatus to provide a source operand for an instruction in a processor | Gary N. Hammond, Carl Scafidi | 2008-07-01 |
| 7383468 | Apparatus and method for protecting critical resources against soft errors in high performance microprocessor | Nhon Quach, Chakravarthy Kosaraju, Venkatesh Nagapudi | 2008-06-03 |