Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7802073 | Virtual core management | Yu Qing Cheng, John G. Favor, Carlos Puchol, Seungyoon Peter Song, Peter N. Glaskowsky +2 more | 2010-09-21 |
| 7389403 | Adaptive computing ensemble microprocessor architecture | John G. Favor, Peter N. Glaskowsky, Seungyoon Peter Song | 2008-06-17 |
| 7010671 | Computer system and method for executing interrupt instructions in two operating modes | John H. Crawford | 2006-03-07 |
| 6584558 | Article for providing event handling functionality in a processor supporting different instruction sets | Gary N. Hammond, Kevin C. Kahn, Harsh Sharangpani | 2003-06-24 |
| 6408386 | Method and apparatus for providing event handling functionality in a computer system | Gary N. Hammond, Kevin C. Kahn, Harsh Sharangpani | 2002-06-18 |
| 6385718 | Computer system and method for executing interrupt instructions in operating modes | John H. Crawford | 2002-05-07 |
| 6219774 | Address translation with/bypassing intermediate segmentation translation to accommodate two different instruction set architecture | Gary N. Hammond, Kevin C. Kahn, Harsh Sharangpani | 2001-04-17 |
| 6052801 | Method and apparatus for providing breakpoints on a selectable address range | Gary N. Hammond | 2000-04-18 |
| 5991874 | Conditional move using a compare instruction generating a condition field | Jack Mills | 1999-11-23 |
| 5958037 | Apparatus and method for identifying the features and the origin of a computer microprocessor | Robert S. Dreyer, William M. Corwin, Tsu-Hua Wang, Daniel G. Lau, Frederick J. Pollack | 1999-09-28 |
| 5802605 | Physical address size selection and page size selection in an address translator | Kenneth D. Shoemaker, Kevin C. Kahn, Konrad K. Lai | 1998-09-01 |
| 5790834 | Apparatus and method using an ID instruction to identify a computer microprocessor | Robert S. Dreyer | 1998-08-04 |
| 5774686 | Method and apparatus for providing two system architectures in a processor | Gary N. Hammond, Kevin C. Kahn, Harsh Sharangpani | 1998-06-30 |
| 5764959 | Adaptive 128-bit floating point load and store instructions for quad-precision compatibility | Harshvardhan Sharangpani, Hans Mulder | 1998-06-09 |
| 5740413 | Method and apparatus for providing address breakpoints, branch breakpoints, and single stepping | Gary N. Hammond | 1998-04-14 |
| 5729724 | Adaptive 128-bit floating point load and store operations for quadruple precision compatibility | Harshvardhan Sharangpani, Hans Mulder | 1998-03-17 |
| 5692167 | Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor | Edward T. Grochowski | 1997-11-25 |
| 5675825 | Apparatus and method for identifying a computer microprocessor | Robert S. Dreyer | 1997-10-07 |
| 5671435 | Technique for software to identify features implemented in a processor | — | 1997-09-23 |
| 5669011 | Partially decoded instruction cache | Dror Avnon, Amos Ben-Meir, Ran Talmudi | 1997-09-16 |
| 5659679 | Method and apparatus for providing breakpoints on taken jumps and for providing software profiling in a computer system | Gary N. Hammond | 1997-08-19 |
| 5657253 | Apparatus for monitoring the performance of a microprocessor | Robert S. Dreyer | 1997-08-12 |
| 5638525 | Processor capable of executing programs that contain RISC and CISC instructions | Gary N. Hammond, Kevin C. Kahn | 1997-06-10 |
| 5621886 | Method and apparatus for providing efficient software debugging | Gary N. Hammond | 1997-04-15 |
| 5617554 | Physical address size selection and page size selection in an address translator | Kenneth D. Shoemaker, Kevin C. Kahn, Konrad K. Lai | 1997-04-01 |