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Multi-protocol I/O interconnect including a switching fabric |
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2018-10-23 |
| 9565132 |
Multi-protocol I/O interconnect including a switching fabric |
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2017-02-07 |
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Multi-protocol tunneling over an I/O interconnect |
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Multi-protocol I/O interconnect architecture |
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2016-02-02 |
| 9047222 |
Unified multi-transport medium connector architecture |
Prashant R. Chandra, Ajay V. Bhatt, Steven B. McGowan |
2015-06-02 |
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Multi-protocol I/O interconnect flow control |
Prashant R. Chandra |
2014-10-07 |
| 8775713 |
Multi-protocol tunneling over an I/O interconnect |
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2014-07-08 |
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Unified multi-transport medium connector architecture |
Prashant R. Chandra, Ajay V. Bhatt, Steve McGowan |
2014-04-15 |
| 7116670 |
Method and apparatus for extending point-to-point/asynchronous transfer mode services to client computer systems |
Tsung-Yuan C. Tai, David B. Andersen, Charles L. Brabenac |
2006-10-03 |
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Method and apparatus for extending point-to-point/asynchronous transfer mode services to client computer systems |
Tsung-Yuan C. Tai, David B. Andersen, Charles L. Brabenac |
2006-05-16 |
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Extending point-to-point/asynchronous transfer mode services to client computer systems |
Tsung-Yuan C. Tai, David B. Andersen, Charles L. Brabenac |
2005-08-02 |
| 6795438 |
Method and apparatus for extending point-to-point/asynchronous transfer mode services to client computer systems |
Tsung-Yuan C. Tai, David B. Andersen, Charles L. Brabenac |
2004-09-21 |
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Article for providing event handling functionality in a processor supporting different instruction sets |
Gary N. Hammond, Donald B. Alpert, Harsh Sharangpani |
2003-06-24 |
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Method and apparatus for providing event handling functionality in a computer system |
Gary N. Hammond, Donald B. Alpert, Harsh Sharangpani |
2002-06-18 |
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Address translation with/bypassing intermediate segmentation translation to accommodate two different instruction set architecture |
Gary N. Hammond, Donald B. Alpert, Harsh Sharangpani |
2001-04-17 |
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System for performing DMA transfer with a pipeline control switching such that the first storage area contains location of a buffer for subsequent transfer |
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1998-10-27 |
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Physical address size selection and page size selection in an address translator |
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1998-09-01 |
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Method and apparatus for providing two system architectures in a processor |
Gary N. Hammond, Donald B. Alpert, Harsh Sharangpani |
1998-06-30 |
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Processor capable of executing programs that contain RISC and CISC instructions |
Gary N. Hammond, Donald B. Alpert |
1997-06-10 |
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Static and dynamic scheduling in an asynchronous transfer mode communication network |
David A. Eckhardt |
1997-04-08 |
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Physical address size selection and page size selection in an address translator |
Donald B. Alpert, Kenneth D. Shoemaker, Konrad K. Lai |
1997-04-01 |
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Multi-processor programmable interrupt controller system |
David G. Carson, Herman D. D'Hooge |
1994-02-01 |
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Input/output data processing system |
John A. Bayliss, George W. Cox, Bert E. Forbes |
1982-02-09 |