AB

Amos Ben-Meir

AM AMD: 17 patents #646 of 9,279Top 7%
NS National Semiconductor: 2 patents #867 of 2,238Top 40%
AC Ampere Computing: 1 patents #52 of 94Top 60%
AC Applied Micro Circuits: 1 patents #192 of 311Top 65%
Overall (All Time): #208,341 of 4,157,543Top 6%
21
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10210096 Multi-stage address translation for a computing device — 2019-02-19
9058284 Method and apparatus for performing table lookup John G. Favor 2015-06-16
6253306 Prefetch instruction mechanism for processor John G. Favor 2001-06-26
6195744 Unified multi-function operation scheduler for out-of-order execution in a superscaler processor John G. Favor, Warren G. Stapleton 2001-02-27
6194927 Apparatus and method for a coincident rising edge detection circuit Matthew P. Crowley 2001-02-27
6161173 Integration of multi-stage execution units with a scheduler for single-stage execution units Ravi Krishna, John G. Favor 2000-12-12
6047382 Processor with short set-up and hold times for bus signals Reading Maley, Anil Mehta 2000-04-04
6038657 Scan chains for out-of-order load/store execution control John G. Favor, Warren G. Stapleton, Jeffrey E. Trull, Mark E. Roberts 2000-03-14
5964884 Self-timed pulse control circuit Hamid Partovi, John C. Holst 1999-10-12
5920515 Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device Imtiaz P. Shaik, Dennis L. Wendell, Benjamin Wong, John C. Holst, Donald A. Draper +1 more 1999-07-06
5915107 Cross clock domain clocking for a system using two clock frequencies where one frequency is fractional multiple of the other Reading Maley, Anil Mehta 1999-06-22
5898640 Even bus clock circuit Matthew P. Crowley 1999-04-27
5884059 Unified multi-function operation scheduler for out-of-order execution in a superscalar processor John G. Favor, Warren G. Stapleton 1999-03-16
5881261 Processing system that rapidly indentifies first or second operations of selected types for execution John G. Favor, Jeffrey E. Trull 1999-03-09
5826073 Self-modifying code handling system John G. Favor 1998-10-20
5809273 Instruction predecode and multiple instruction decode John G. Favor 1998-09-15
5799165 Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay John G. Favor 1998-08-25
5754812 Out-of-order load/store execution control John G. Favor, Warren G. Stapleton, Jeffrey E. Trull, Mark E. Roberts 1998-05-19
5745724 Scan chain for rapidly identifying first or second objects of selected types in a sequential list John G. Favor, Jeffrey E. Trull 1998-04-28
5669011 Partially decoded instruction cache Donald B. Alpert, Dror Avnon, Ran Talmudi 1997-09-16
5481751 Apparatus and method for storing partially-decoded instructions in the instruction cache of a CPU having multiple execution units Donald B. Alpert, Dror Avnon, Ran Talmudi 1996-01-02