Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7188325 | Method for selecting transistor threshold voltages in an integrated circuit | Marius Evers, Alper Halbutogullari, Robert W. Williams | 2007-03-06 |
| 6487653 | Method and apparatus for denormal load handling | Stuart F. Oberman, Stephan G. Meier | 2002-11-26 |
| 6460130 | Detecting full conditions in a queue | Eric W. Mahurin | 2002-10-01 |
| 6405305 | Rapid execution of floating point load control word instructions | Stephan G. Meier, Derrick R. Meyer, Norbert Juffa | 2002-06-11 |
| 6247114 | Rapid selection of oldest eligible entry in a queue | — | 2001-06-12 |
| 6185672 | Method and apparatus for instruction queue compression | — | 2001-02-06 |
| 6038657 | Scan chains for out-of-order load/store execution control | John G. Favor, Amos Ben-Meir, Warren G. Stapleton, Mark E. Roberts | 2000-03-14 |
| 5881261 | Processing system that rapidly indentifies first or second operations of selected types for execution | John G. Favor, Amos Ben-Meir | 1999-03-09 |
| 5835747 | Hierarchical scan logic for out-of-order load/store execution control | — | 1998-11-10 |
| 5754812 | Out-of-order load/store execution control | John G. Favor, Amos Ben-Meir, Warren G. Stapleton, Mark E. Roberts | 1998-05-19 |
| 5745724 | Scan chain for rapidly identifying first or second objects of selected types in a sequential list | John G. Favor, Amos Ben-Meir | 1998-04-28 |
| 5497477 | System and method for replacing a data entry in a cache memory | — | 1996-03-05 |