| 10318676 |
Techniques for statistical frequency enhancement of statically timed designs |
Alfred Yeung, Subbayyan Venkatsan, Vamsi Srikantam |
2019-06-11 |
|
| 10162373 |
Variation immune on-die voltage droop detector |
Yan Chong, Luca Ravezzi, Alfred Yeung |
2018-12-25 |
|
| 10145868 |
Self-referenced on-die voltage droop detector |
Yan Chong, Luca Ravezzi, Alfred Yeung |
2018-12-04 |
|
| 9568511 |
High frequency voltage supply monitor |
Luca Ravezzi, Qawi Harvard |
2017-02-14 |
|
| 8618856 |
Shadow latch |
Alfred Yeung, John Ngai, Ronen Cohen |
2013-12-31 |
$10,581,000 |
| 8604854 |
Pseudo single-phase flip-flop (PSP-FF) |
Alfred Yeung, Luca Ravezzi, John Ngai |
2013-12-10 |
$3,267,000 |
| 8497721 |
Pass gate shadow latch |
Alfred Yeung, John Ngai, Ronen Cohen |
2013-07-30 |
$4,982,000 |
| 8421514 |
Hazard-free minimal-latency flip-flop (HFML-FF) |
Alfred Yeung, Luca Ravezzi, John Ngai |
2013-04-16 |
$5,230,000 |
| 8384421 |
Digital CMOS circuit with noise cancellation |
Luca Ravezzi |
2013-02-26 |
$3,001,000 |
| 7991573 |
Integrated circuit including calibration circuit |
Russell Homer, Luca Ravezzi |
2011-08-02 |
|
| 7813289 |
Electrical idle detection circuit including input signal rectifier |
Karthik Gopalakrishnan, Luca Ravezzi |
2010-10-12 |
|
| 7733815 |
Data sampler including a first stage and a second stage |
Karthik Gopalakrishnan, Luca Ravezzi, Sivaraman Chokkalingam, Edoardo Prete |
2010-06-08 |
|
| 7681063 |
Clock data recovery circuit with circuit loop disablement |
Luca Ravezzi, Karthik Gopalakrishnan, Andreas Blum, Paul Lindt |
2010-03-16 |
|
| 7480358 |
CDR-based clock synthesis |
William P. Evans |
2009-01-20 |
$223,000 |
| 7061337 |
Amplitude control circuit |
Sivaraman Chokkalingam, Karthik Gopalakrishnan |
2006-06-13 |
$121,000 |
| 6593632 |
Interconnect methodology employing a low dielectric constant etch stop layer |
Steven C. Avanzino, Minh Van Ngo, Angela T. Hui, Chun Jiang |
2003-07-15 |
$1,952,000 |
| 6440839 |
Selective air gap insulation |
Chun Jiang, Bill Liu |
2002-08-27 |
$1,474,000 |
| 6278308 |
Low-power flip-flop circuit employing an asymmetric differential stage |
Michael L. Golden, John Yong |
2001-08-21 |
$5,111,000 |
| 6137126 |
Method to reduce gate-to-local interconnect capacitance using a low dielectric constant material for LDD spacer |
Steven C. Avanzino, Minh Van Ngo, Angela T. Hui, Chun Jiang |
2000-10-24 |
$7,838,000 |
| 6087872 |
Dynamic latch circuitry |
Robert C. Burd, Udin Salim, Frederick Daniel Weber, Luigi Di Gregorio, Donald A. Draper |
2000-07-11 |
$9,020,000 |
| 6081136 |
Dynamic NOR gates for NAND decode |
Rajesh Khanna |
2000-06-27 |
$12,313,000 |
| 6078487 |
Electro-static discharge protection device having a modulated control input terminal |
Kaizad Mistry, David Benjamin Krakauer, William McGee |
2000-06-20 |
|
| 5990717 |
Latching method |
Robert C. Burd, Udin Salim, Frederick Daniel Weber, Luigi Di Gregorio, Donald A. Draper |
1999-11-23 |
$2,771,000 |
| 5986490 |
Amplifier-based flip-flop elements |
Yi-Ren Hwang, Dennis L. Wendell |
1999-11-16 |
$2,707,000 |
| 5964884 |
Self-timed pulse control circuit |
John C. Holst, Amos Ben-Meir |
1999-10-12 |
$2,065,000 |
