Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10318696 | Efficient techniques for process variation reduction for static timing analysis | Alfred Yeung, Subbayyan Venkatesan, Manoj N. Kulkarni, Ojas Dharia | 2019-06-11 |
| 10318676 | Techniques for statistical frequency enhancement of statically timed designs | Alfred Yeung, Subbayyan Venkatsan, Hamid Partovi | 2019-06-11 |
| 7450659 | Digital modulator employing a polyphase up-converter structure | Paul L. Corredoura | 2008-11-11 |
| 7411437 | Triggering events at fractions of a clock cycle | Dietrich W. Vook, Andrew D. Fernandez | 2008-08-12 |
| 7339853 | Time stamping events for fractions of a clock cycle | Andew David Fernandez, Dietrich W. Vook | 2008-03-04 |
| 7148828 | System and method for timing calibration of time-interleaved data converters | Andrew D. Fernandez, Robert M. R. Neff, Kenneth D. Poulton | 2006-12-12 |
| 7096374 | Method and apparatus for defining an input state vector that achieves low power consumption in digital circuit in an idle state | Thomas Edward Kopley | 2006-08-22 |
| 7085942 | Method and apparatus for defining an input state vector that achieves low power consumption in a digital circuit in an idle state | Thomas Edward Kopley | 2006-08-01 |
| 6822481 | Method and apparatus for clock gating clock trees to reduce power dissipation | Airell R. Clark, II | 2004-11-23 |
| 6601230 | Low power circuit design through judicious module selection | — | 2003-07-29 |
| 6275083 | Low operational power, low leakage power D-type flip-flop | Mario Martinez | 2001-08-14 |