Issued Patents All Time
Showing 25 most recent of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12237387 | Method of spacer formation with straight sidewall of memory cells | Scott A. Bell, Shenqing Fang | 2025-02-25 |
| 11830942 | Contacts for semiconductor devices | Wenmei Li, Minh Van Ngo, Amol Joshi, Kuo-Tung Chang | 2023-11-28 |
| 10944000 | Contacts for semiconductor devices | Wenmei Li, Minh Van Ngo, Amol Joshi, Kuo-Tung Chang | 2021-03-09 |
| 10593688 | Split-gate semiconductor device with L-shaped gate | Scott A. Bell, Chun Chen, Lei Xue, Shenqing Fang | 2020-03-17 |
| 10516044 | Contacts for semiconductor devices | Wenmei Li, Minh Van Ngo, Amol Joshi, Kuo-Tung Chang | 2019-12-24 |
| 10020316 | Split-gate semiconductor device with L-shaped gate | Scott A. Bell, Chun Chen, Lei Xue, Shenqing Fang | 2018-07-10 |
| 9673206 | Buried hard mask for embedded semiconductor device patterning | Scott A. Bell, Simon S. Chan | 2017-06-06 |
| 9589805 | Split-gate semiconductor device with L-shaped gate | Scott A. Bell, Chun Chen, Lei Xue, Shenqing Fang | 2017-03-07 |
| 9466496 | Spacer formation with straight sidewall | Scott A. Bell, Shenqing Fang | 2016-10-11 |
| 9455352 | HTO offset for long leffective, better device performance | Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan P. Choi | 2016-09-27 |
| 9431503 | Integrating transistors with different poly-silicon heights on the same die | Chuan Lin, Hidehiko Shiraiwa, Bradley Marc Davis, Lei Xue, Simon S. Chan +2 more | 2016-08-30 |
| 9318498 | Buried hard mask for embedded semiconductor device patterning | Scott A. Bell, Simon S. Chan | 2016-04-19 |
| 9245895 | Oro and orpro with bit line trench to suppress transport program disturb | Ning Cheng, Kuo-Tung Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue +3 more | 2016-01-26 |
| 8975185 | Forming charge trap separation in a flash memory semiconductor device | — | 2015-03-10 |
| 8836012 | Spacer design to prevent trapped electrons | — | 2014-09-16 |
| 8815727 | Integrated circuit with metal and semi-conducting gate | Mark S. Chang, Kuo-Tung Chang, Scott A. Bell | 2014-08-26 |
| 8790530 | Planar cell ONO cut using in-situ polymer deposition and etch | Gang Xue | 2014-07-29 |
| 8759894 | System and method for reducing cross-coupling noise between charge storage elements in a semiconductor device | Yider Wu, Hiroyuki Ogawa, Unsoon Kim | 2014-06-24 |
| 8658496 | Etch stop layer for memory cell reliability improvement | Hiroyuki Kinoshita, Hsiao-Han Thio, Kuo-Tung Chang, Minh Van Ngo, Hiroyuki Ogawa | 2014-02-25 |
| 8653581 | HTO offset for long Leffective, better device performance | Ning Cheng, Huaqiang Wu, Hiro Kinoshita, Jihwan P. Choi | 2014-02-18 |
| 8652907 | Integrating transistors with different poly-silicon heights on the same die | Chuan Lin, Hidehiko Shiraiwa, Bradley Marc Davis, Lei Xue, Simon S. Chan +2 more | 2014-02-18 |
| 8614475 | Void free interlayer dielectric | Minh Van Ngo, Hirokazu Tokuno, Wenmei Li, Hsiao-Han Thio | 2013-12-24 |
| 8598005 | Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices | Simon S. Chan, Hidehiko Shiraiwa, Chuan Lin, Lei Xue, Kenichi Ohtsuka | 2013-12-03 |
| 8598645 | System and method for improving mesa width in a semiconductor device | Unsoon Kim, Yider Wu, Kuo-Tung Chang, Hiroyuki Kinoshita | 2013-12-03 |
| 8564041 | Contacts for semiconductor devices | Wenmei Li, Minh Van Ngo, Amol Joshi, Kuo-Tung Chang | 2013-10-22 |