Issued Patents All Time
Showing 26–50 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8551858 | Self-aligned SI rich nitride charge trap layer isolation for charge trap flash memory | Shenqing Fang, Shao-Yu Ting, Inkuk Kang, Gang Xue | 2013-10-08 |
| 8445372 | Selective silicide formation using resist etch back | Kyunghoon Min, Hiroyuki Kinoshita, Ning Cheng, Mark S. Chang | 2013-05-21 |
| 8409994 | Gate trim process using either wet etch or dry etch approach to target CD for selected transistors | Bradley Marc Davis, Jihwan P. Choi | 2013-04-02 |
| 8384146 | Methods for forming a memory cell having a top oxide spacer | Shenqing Fang, Gang Xue, Alexander H. Nickel, Kashmir Sahota, Scott A. Bell +2 more | 2013-02-26 |
| 8367493 | Void free interlayer dielectric | Minh Van Ngo, Hirokazu Tokuno, Wenmei Li, Hsiao-Han Thio | 2013-02-05 |
| 8349685 | Dual spacer formation in flash memory | Shenqing Fang | 2013-01-08 |
| 8319266 | Etch stop layer for memory cell reliability improvement | Hiroyuki Kinoshita, Hsiao-Han Thio, Kuo-Tung Chang, Minh Van Ngo, Hiroyuki Ogawa | 2012-11-27 |
| 8283718 | Integrated circuit system with metal and semi-conducting gate | Mark S. Chang, Kuo-Tung Chang, Scott A. Bell | 2012-10-09 |
| 8202779 | Methods for forming a memory cell having a top oxide spacer | Shenqing Fang, Gang Xue, Alexander H. Nickel, Kashmir Sahota, Scott A. Bell +2 more | 2012-06-19 |
| 8114736 | Integrated circuit system with memory system | Simon S. Chan, Hidehiko Shiraiwa, Kuo-Tung Chang | 2012-02-14 |
| 8093646 | Flash memory device and method of forming the same with improved gate breakdown and endurance | Yider Wu | 2012-01-10 |
| 8067314 | Gate trim process using either wet etch or dry etch approach to target CD for selected transistors | Bradley Marc Davis, Jihwan P. Choi | 2011-11-29 |
| 8035153 | Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications | Shenqing Fang, Jihwan P. Choi, Calvin T. Gabriel, Fei Wang, Alexander H. Nickel +4 more | 2011-10-11 |
| 8022468 | Ultraviolet radiation blocking interlayer dielectric | Minh Van Ngo, Wenmei Li, Jeffrey A. Shields, Ning Cheng, Cinti X. Chen | 2011-09-20 |
| 8012830 | ORO and ORPRO with bit line trench to suppress transport program disturb | Ning Cheng, Kuo-Tung Chang, Hiro Kinoshita, Chih-Yuh Yang, Lei Xue +3 more | 2011-09-06 |
| 7985687 | System and method for improving reliability in a semiconductor device | Hiroyuki Kinoshita, Unsoon Kim, Harpreet Sachar | 2011-07-26 |
| 7977797 | Integrated circuit with contact region and multiple etch stop insulation layer | Wenmei Li, Dawn Hopper, Kouros Ghandehari | 2011-07-12 |
| 7972951 | Memory device etch methods | Jihwan P. Choi | 2011-07-05 |
| 7951675 | SI trench between bitline HDP for BVDSS improvement | Lei Xue, Aimin Xing, Chih-Yuh Yang, Chungho Lee | 2011-05-31 |
| 7927723 | Film stacks to prevent UV-induced device damage | Ning Cheng, Minh Van Ngo, Hirokazu Tokuno, Wenmei Li | 2011-04-19 |
| 7906807 | Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics | Ning Cheng, Calvin T. Gabriel, Lei Xue, Harpreet Sachar, Phillip Jones +3 more | 2011-03-15 |
| 7842618 | System and method for improving mesa width in a semiconductor device | Unsoon Kim, Yider Wu, Kuo-Tung Chang, Hiroyuki Kinoshita | 2010-11-30 |
| 7785965 | Dual storage node memory devices and methods for fabricating the same | Unsoon Kim, Kyunghoon Min, Ning Cheng, Hiroyuki Kinoshita, Sugino Rinji +3 more | 2010-08-31 |
| 7776688 | Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics | Ning Cheng, Calvin T. Gabriel, Lei Xue, Harpreet Sachar, Phillip Jones +3 more | 2010-08-17 |
| 7732276 | Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications | Shenqing Fang, Jihwan P. Choi, Calvin T. Gabriel, Fei Wang, Alexander H. Nickel +4 more | 2010-06-08 |