Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8384146 | Methods for forming a memory cell having a top oxide spacer | Shenqing Fang, Angela T. Hui, Gang Xue, Alexander H. Nickel, Scott A. Bell +2 more | 2013-02-26 |
| 8202779 | Methods for forming a memory cell having a top oxide spacer | Shenqing Fang, Angela T. Hui, Gang Xue, Alexander H. Nickel, Scott A. Bell +2 more | 2012-06-19 |
| 7449413 | Method for effectively removing polysilicon nodule defects | Krishnashree Achuthan | 2008-11-11 |
| 7358191 | Method for decreasing sheet resistivity variations of an interconnect metal layer | Krishnashree Achuthan, Brad Davis, James J. Xie | 2008-04-15 |
| 7307002 | Non-critical complementary masking method for poly-1 definition in flash memory device fabrication | Unsoon Kim, Hiroyuki Kinoshita, Yu Sun, Krishnashree Achuthan, Christopher H. Raeder +2 more | 2007-12-11 |
| 7294573 | Method for controlling poly 1 thickness and uniformity in a memory array fabrication process | Krishnashree Achuthan, Unsoon Kim, Patriz C. Regalado | 2007-11-13 |
| 7208382 | Semiconductor device with high conductivity region using shallow trench | Jeffrey P. Erhardt, Emmanuil H. Lingunis, Nga-Ching Wong | 2007-04-24 |
| 7141502 | Slurry-less polishing for removal of excess interconnect material during fabrication of a silicon integrated circuit | James J. Xie, Richard J. Huang | 2006-11-28 |
| 7077728 | Method for reducing edge array erosion in a high-density array | Krishnashree Achuthan | 2006-07-18 |
| 7052969 | Method for semiconductor wafer planarization by isolation material growth | Krishnashree Achuthan | 2006-05-30 |
| 7053446 | Memory wordline spacer | Tazrien Kamal, Mark T. Ramsbey | 2006-05-30 |
| 6927113 | Semiconductor component and method of manufacture | Jeremy I. Martin, Richard J. Huang, James J. Xie | 2005-08-09 |
| 6773988 | Memory wordline spacer | Tazrien Kamal, Mark T. Ramsbey | 2004-08-10 |
| 6770523 | Method for semiconductor wafer planarization by CMP stop layer formation | Jeffrey P. Erhardt, Arvind Halliyal, Minh Van Ngo, Krishnashree Achuthan | 2004-08-03 |
| 6723605 | Method for manufacturing memory with high conductivity bitline and shallow trench isolation integration | Jeffrey P. Erhardt | 2004-04-20 |
| 6720264 | Prevention of precipitation defects on copper interconnects during CMP by use of solutions containing organic compounds with silica adsorption and copper corrosion inhibiting properties | Diana M. Schonauer, Johannes Groschopf, Gerd Marxsen, Steven C. Avanzino | 2004-04-13 |
| 6699785 | Conductor abrasiveless chemical-mechanical polishing in integrated circuit interconnects | Kai Yang, Steven C. Avanzino | 2004-03-02 |
| 6613646 | Methods for reduced trench isolation step height | Krishnashree Achuthan | 2003-09-02 |
| 6569747 | Methods for trench isolation with reduced step height | Krishnashree Achuthan | 2003-05-27 |
| 6518185 | Integration scheme for non-feature-size dependent cu-alloy introduction | Pin-Chin Connie Wang, Fei Wang, Steven C. Avanzino, Amit P. Marathe, Matthew S. Buynoski +2 more | 2003-02-11 |
| 6503418 | Ta barrier slurry containing an organic additive | Diana M. Schonauer, Steven C. Avanzino | 2003-01-07 |
| 6426297 | Differential pressure chemical-mechanical polishing in integrated circuit interconnects | Krishnashree Achuthan, Sergey Lopatin | 2002-07-30 |
| 6413869 | Dielectric protected chemical-mechanical polishing in integrated circuit interconnects | Krishnashree Achuthan, Steven C. Avanzino | 2002-07-02 |
| 6410443 | Method for removing semiconductor ARC using ARC CMP buffing | Steven C. Avanzino, Stephen Keetai Park, David Matsumoto, Mark T. Ramsbey | 2002-06-25 |
| 6380067 | Method for creating partially UV transparent anti-reflective coating for semiconductors | Ramkumar Subramanian, Minh Van Ngo, Suzette K. Pangrle, Christopher F. Lyons | 2002-04-30 |