| 8504679 |
Methods, systems and computer program products for managing execution of information technology (IT) processes |
Edward Spire, Jiebo Guan, Michael Sharpe, Roberto Reiner, Mark Jones |
2013-08-06 |
| 6881665 |
Depth of focus (DOF) for trench-first-via-last (TFVL) damascene processing with hard mask and low viscosity photoresist |
Ting Tsui, Christian Zistl |
2005-04-19 |
| 6756297 |
Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer |
— |
2004-06-29 |
| 6682978 |
Integrated circuit having increased gate coupling capacitance |
Steven C. Avanzino |
2004-01-27 |
| 6576949 |
Integrated circuit having optimized gate coupling capacitance |
— |
2003-06-10 |
| 6562683 |
Bit-line oxidation by removing ONO oxide prior to bit-line implant |
Fei Wang, David K. Foote |
2003-05-13 |
| 6486506 |
Flash memory with less susceptibility to charge gain and charge loss |
Jeffrey A. Shields |
2002-11-26 |
| 6458656 |
Process for creating a flash memory cell using a photoresist flow operation |
George J. Kluth, Bharath Rangarajan |
2002-10-01 |
| 6436766 |
Process for fabricating high density memory cells using a polysilicon hard mask |
Bharath Rangarajan, David K. Foote, Fei Wang, Dawn Hopper, Jack F. Thomas +2 more |
2002-08-20 |
| 6420104 |
Method of reducing contact size by spacer filling |
Bharath Rangarajan, Guarionex Morales |
2002-07-16 |
| 6410443 |
Method for removing semiconductor ARC using ARC CMP buffing |
Steven C. Avanzino, Kashmir Sahota, David Matsumoto, Mark T. Ramsbey |
2002-06-25 |
| 6410388 |
Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device |
George Jonathan Kluth, Arvind Halliyal, David K. Foote |
2002-06-25 |
| 6399446 |
Process for fabricating high density memory cells using a metallic hard mask |
Bharath Rangarajan, David K. Foote, Fei Wang, Dawn Hopper, Jack F. Thomas +2 more |
2002-06-04 |
| 6355555 |
Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer |
— |
2002-03-12 |
| 6306758 |
Multipurpose graded silicon oxynitride cap layer |
— |
2001-10-23 |
| 6303486 |
Method of fabricating copper-based semiconductor devices using a sacrificial dielectric layer and an unconstrained copper anneal |
— |
2001-10-16 |
| 6287917 |
Process for fabricating an MNOS flash memory device |
Tim Thurgate, Bharath Rangarajan |
2001-09-11 |
| 6265306 |
Resist flow method for defining openings for conductive interconnections in a dielectric layer |
Gregory B. Starnes |
2001-07-24 |
| 6265294 |
Integrated circuit having double bottom anti-reflective coating layer |
Guarionex Morales, Bharath Rangarajan, Jeff Shields |
2001-07-24 |
| 6265273 |
Method of forming rectangular shaped spacers |
Steven C. Avanzino, Bharath Rangarajan, Jeffrey A. Shields, Larry Wang, Guarionex Morales |
2001-07-24 |
| 6232635 |
Method to fabricate a high coupling flash cell with less silicide seam problem |
Larry Wang, Steven C. Avanzino, Jeffrey A. Shields |
2001-05-15 |
| 6107169 |
Method for fabricating a doped polysilicon feature in a semiconductor device |
— |
2000-08-22 |
| 6100559 |
Multipurpose graded silicon oxynitride cap layer |
— |
2000-08-08 |